Receive circuit for use in a power converter

Patent metadata

Field	Value
Publication number	US-9276479-B2
Application number	US-201313747071-A
Country	US
Kind code	B2
Filing date	Jan 22, 2013
Priority date	Jan 22, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A receive circuit for use in a power converter controller includes a first amplifier coupled to receive an input pulse. A second amplifier is coupled to a first output of the first amplifier. The first output is coupled to be responsive to the input pulse and to a second output of the second amplifier. An output circuit is coupled to generate an output signal in response to the second output.

First claim

What is claimed is:

1. A receive circuit for use in a power converter controller, comprising:
a first amplifier coupled to receive an input pulse;
a second amplifier coupled to a first output of the first amplifier, wherein the first output is coupled to be responsive to the input pulse and to a second output of the second amplifier;
an output circuit coupled to generate an output signal in response to the second output;
a first pre-bias circuit coupled to reset the first output to a first value in response to the output signal;
a second pre-bias circuit coupled to reset the second output to a second value in response to the output signal; and
a delay circuit coupled to receive the output signal, wherein the delay circuit is coupled to generate a pre-bias control signal responsive to the output signal, and wherein the delay circuit is coupled to the first pre-bias circuit and the second pre-bias circuit, wherein the delay circuit is coupled to generate a pulse of the pre-bias control signal that is delayed from a corresponding pulse of the output signal by at least a pulse width of the input pulse.

2. The receive circuit of claim 1 , wherein the first pre-bias circuit includes a first switch coupled to reset the first output to the first value.

3. The receive circuit of claim 1 , wherein the second pre-bias circuit includes a second switch coupled to reset the second output to the second value.

4. The receive circuit of claim 1 , wherein the second amplifier includes a second amplifier switch coupled to be controlled by the first output of the first amplifier, and wherein the first value is just below a turn-on value of the second amplifier switch.

5. The controller of claim 1 , wherein the first amplifier includes a differential amplifier having a first transistor and a second transistor coupled together at their bases, wherein the first transistor receives the input pulse at an emitter of the first transistor.

6. The controller of claim 1 , wherein the output circuit includes an inverter coupled to compare the output of the second amplifier to a threshold voltage, the inverter further coupled to output the output signal.

7. A power converter, comprising:
an energy transfer element;
a switch coupled to the energy transfer element and coupled to an input of the power converter; and
a controller circuit coupled to control switching of the switch to control a transfer of energy through the energy transfer element from the input of the power converter to an output of the power converter, the controller circuit including a receive circuit including:
a first amplifier coupled to receive an input pulse;
a second amplifier coupled to a first output of the first amplifier, wherein the first output is coupled to be responsive to the input pulse and to a second output of the second amplifier, wherein the second amplifier includes a second amplifier switch coupled to be controlled by the first output of the first amplifier, and wherein, in the absence of the input pulse in the receiver circuit, a first value of the first output is just below a turn-on value of the second amplifier switch; and
an output circuit coupled to generate an output signal in response to the second output.

8. The power converter of claim 7 further comprising a magnetically coupled communication link coupled between a primary side of the power converter and a secondary side of the power converter, wherein the first amplifier is coupled to receive the input pulse via the magnetically coupled communication link.

9. The power converter of claim 7 , wherein the switch is coupled to be responsive to the output signal.

10. The power converter of claim 7 , wherein the receive circuit further comprises:
a first pre-bias circuit coupled to reset the first output to a first value in response to the output signal; and
a second pre-bias circuit coupled to reset a second output of the second amplifier to a second value in response to the output signal.

11. The power converter of claim 10 further comprising a delay circuit coupled to receive the output signal, wherein the delay circuit is coupled to generate a pre-bias control signal responsive to the output signal, and wherein the delay circuit is coupled to the first pre-bias circuit and the second pre-bias circuit.

12. The power converter of claim 11 , wherein the delay circuit is coupled to generate a pulse of the pre-bias control signal that is delayed from a corresponding pulse of the output signal by at least a pulse width of the input pulse.

13. The power converter of claim 10 , wherein the first pre-bias circuit includes a first switch coupled to reset the first output to the first value.

14. The power converter of claim 10 , wherein the second pre-bias circuit includes a second switch coupled to reset the second output to the second value.

15. The power converter of claim 7 , wherein the first amplifier includes a differential amplifier having a first transistor and a second transistor coupled together at their bases, wherein the first transistor receives the input pulse at an emitter of the first transistor.

16. The power converter of claim 7 , wherein the output circuit includes an inverter coupled to compare the output of the second amplifier to a threshold voltage, the inverter further coupled to output the output signal.

17. The power converter of claim 7 , wherein the receive circuit is coupled to receive the input pulse from a transmitter, wherein the receive circuit is disposed on a separate semiconductor die.

18. The power converter of claim 17 , wherein the receive circuit is disposed on a first die and the transmitter is disposed on a second die, and wherein the first die is disposed on a primary side of the power converter and the transmitter is disposed on a secondary side of the power converter.

Assignees

• Power Integrations Inc

Inventors

• Djenguerian Alex B
• Liu Sheng
• Lund Leif

Classifications

• H02M3/33592 Primary

  having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer · CPC title

• H03G1/00

  Details of arrangements for controlling amplification · CPC title

• H02M3/335 Primary

  using semiconductor devices only · CPC title

• Y02B70/1475

  Cross-Sectional Technologies · mapped topic

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title