Semiconductor integrated circuit and operating method thereof

Patent metadata

Field	Value
Publication number	US-9276404-B2
Application number	US-201313899601-A
Country	US
Kind code	B2
Filing date	May 22, 2013
Priority date	May 28, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A semiconductor integrated circuit and its operating method are provided. The present circuit has first and second supply terminals capable of supplying first and second power supply voltages respectively, an input voltage selection circuit coupled to the first and second supply terminals, and first and second power supply switches. The input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit and a control circuit. When the supply of the first or second power supply voltage to one of both supply terminals is detected upon completion of a power on reset operation, one of both power supply switches and the other thereof are controlled to on and off respectively. When the supply of both power supply voltages to both supply terminals is detected, the one thereof and the other thereof are respectively controlled to on and off according to the preset order of precedence.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a first supply terminal capable of supplying a first power supply voltage;
a second supply terminal capable of supplying a second power supply voltage;
an input voltage selection circuit coupled to the first supply terminal and the second supply terminal;
a first power supply switch; and
a second power supply switch,
wherein the input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit and a control circuit,
wherein in response to the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal, the power-on reset circuit generates a power on reset signal,
wherein the input voltage detection circuit generates a first voltage detection output signal in response to the supply of the first power supply voltage to the first supply terminal and generates a second voltage detection output signal in response to the supply of the second power supply voltage to the second supply terminal,
wherein the control circuit controls the first power supply switch and the second power supply switch in response to the power on reset signal, the first voltage detection output signal and the second voltage detection output signal,
wherein the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal at a timing of a change in the level of the power on reset signal responsive to the end of a power on reset operation of the power-on reset circuit,
wherein in a first case where at the timing of the change in the level of the power on reset signal, the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal but does not detect the supply of the second power supply voltage to the second supply terminal, the control circuit controls the first power supply switch and the second power supply switch to an on state and an off state respectively after the end of the power on reset operation,
wherein the first power supply switch controlled to the on state supplies the first power supply voltage supplied to the first supply terminal to a load by the control of the first power supply switch and the second power supply switch to the on state and the off state respectively after the end of the power on reset operation,
wherein in a second case where at the timing of the change in the level of the power on reset signal, the input voltage detection circuit detects the supply of the second power supply voltage to the second supply terminal but does not detect the supply of the first power supply voltage to the first supply terminal, the control circuit controls the first power supply switch and the second power supply switch to an off state and an on state respectively after the end of the power on reset operation,
wherein the second power supply switch controlled to the on state supplies the second power supply voltage supplied to the second supply terminal to the load by the control of the first power supply switch and the second power supply switch to the off state and the on state respectively after the end of the power on reset operation,
wherein in a third case where at the timing of the change in the level of the power on reset signal, the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal, the control circuit controls one of the first power supply switch and the second power supply switch and the other thereof to an on state and an off state respectively after the end of the power on reset operation,
wherein in the third case, the one of the first power supply switch and the second power supply switch and the other thereof are respectively controlled to the on state and the off state in accordance with the order of precedence set to the control circuit in advance, and
wherein the one thereof controlled to the on state supplies the first power supply voltage or the second power supply voltage supplied to the first supply terminal or the second supply terminal to the load.

2. The semiconductor integrated circuit according to claim 1 , further including a first external output terminal and a second external output terminal which supply the first power supply voltage or the second power supply voltage to a first external load and a second external load taken as the load respectively; and
an output P channel MOS transistor coupled between the first external output terminal and the second external output terminal,
wherein when either of the first power supply switch and the second power supply switch is controlled to an on state after the end of the power on reset operation, the output P channel MOS transistor is controlled to an on state by the control circuit, and
wherein the control of the output P channel MOS transistor to the on state enables the first power supply voltage or the second power supply voltage to be supplied to the second external load through the output P channel MOS transistor and the second external output terminal.

3. The semiconductor integrated circuit according to claim 2 , wherein the first external output terminal is configured so as to be capable of supplying the first power supply voltage or the second power supply voltage to the first external load corresponding to another semiconductor integrated circuit taken as an active device, and
wherein the output P channel MOS transistor and the second external output terminal are configured so as to be capable of supplying the first power supply voltage or the second power supply voltage to the second external load taken as a battery.

4. The semiconductor integrated circuit according to claim 3 , wherein the input voltage selection circuit further includes an input voltage selection switch and a gate drive circuit,
wherein the input voltage selection switch includes a first input P channel MOS transistor and a second input P channel MOS transistor, the first input P channel MOS transistor having a source coupled to the first supply terminal and the second input P channel MOS transistor having a source coupled to the second supply terminal,
wherein during a power on reset period of the power-on reset circuit, the gate drive circuit controls both of the first and second input P channel MOS transistors of the input voltage selection switch to an on state, and
wherein during the power on reset period, an operating voltage to be supplied to the power-on reset circuit is generated from a drain of the first input P channel MOS transistor or a drain of the second input P channel MOS transistor.

5. The semiconductor integrated circuit according to claim 4 , wherein in the first case, the gate drive circuit controls the first and second input P channel MOS transistors of the input voltage selection switch to an on state and an off state respectively,
wherein in the second case, the gate drive circuit controls the first and second input P channel MOS transistors of the input voltage selection switch to an on state and an off state respectively, and
wherein in the third case, the gate drive circuit controls one of the first and second input P channel MOS transistors of the input voltage selection switch and the other thereof to an on state and an off state respectively in accordance with the order of precedence set to the control circuit in advance.

6. The semiconductor integrated circuit according to claim 5 , wherein the input voltage selection circuit further includes a voltage comparison/selection circuit having a firs

Assignees

• Renesas Electronics Corp

Inventors

• Kayama Masanori

Classifications

• H02J2207/40

  adapted for charging from various sources, e.g. AC, DC or multivoltage · CPC title

• H03K17/223

  in field-effect transistor switches · CPC title

• H02J9/06

  with automatic change-over {, e.g. UPS systems} · CPC title

• G06F1/263

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• G06F1/266

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title