Logic drive using standard commodity programmable logic ic chips comprising non-volatile random access memory cells
US-2024380401-A1 · Nov 14, 2024 · US
US9276198B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9276198-B2 |
| Application number | US-201313967340-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 14, 2013 |
| Priority date | Aug 30, 2012 |
| Publication date | Mar 1, 2016 |
| Grant date | Mar 1, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A magnetic memory device according to embodiments includes a first reference magnetic layer on a substrate, a second reference magnetic layer on the first reference magnetic layer, a free layer between the first reference magnetic layer and the second reference magnetic layer, a first tunnel barrier layer between the first reference magnetic layer and the free layer, and a second tunnel barrier layer between the second reference magnetic layer and the free layer. The first reference magnetic, second reference magnetic and free layers each have a magnetization direction substantially perpendicular to a top surface of the substrate. A resistance-area product (RA) value of the first tunnel barrier layer is greater than that of the second tunnel barrier layer.
Opening claim text (preview).
What is claimed is: 1. A magnetic memory device comprising: a first tunnel barrier layer disposed at a first height from a substrate; a second tunnel barrier layer disposed at a second height greater than the first height from the substrate, the second tunnel barrier layer thinner than the first tunnel barrier layer; a free layer disposed between the first tunnel barrier layer and the second tunnel barrier layer; a first reference magnetic layer disposed under the first tunnel barrier layer; a second reference magnetic layer disposed over the second tunnel barrier layer, wherein the first reference magnetic layer, the second reference magnetic layer, and the free layer each have a magnetization direction substantially perpendicular to a top surface of the semiconductor substrate, and wherein the first and second tunnel barrier layers are formed of magnesium oxide (MgO). 2. The magnetic memory device of claim 1 , wherein a resistance-area product (RA) value of the first tunnel barrier layer is greater than a RA value of the second tunnel barrier layer. 3. The magnetic memory device of claim 1 , wherein a ratio of a resistance-area product (RA) value of the second tunnel barrier layer to a RA value of the first tunnel barrier layer has a range of about 1:5 to about 1:10. 4. The magnetic memory device of claim 1 , wherein the first and second tunnel barrier layers are formed of magnesium oxide (MgO) having a (001) crystal plane substantially parallel to a top surface of the substrate. 5. The magnetic memory device of claim 1 , wherein the first reference magnetic layer is in contact with a first surface of the first tunnel barrier layer; wherein the free layer is in contact with a second surface opposite to the first surface of the first tunnel barrier layer; and wherein a top surface of the free layer has a (001) crystal plane. 6. The magnetic memory device of claim 1 , wherein the free layer is formed of a magnetic material aligned in a (001) crystal plane of the first tunnel barrier layer. 7. The magnetic memory device of claim 1 , further comprising: a crystalline magnetic layer disposed between the first reference magnetic layer and the first tunnel barrier layer, between the free layer and the first tunnel barrier layer, between the second reference magnetic layer and the second tunnel barrier layer, and/or between the free layer and the second tunnel barrier layer. 8. The magnetic memory device of claim 7 , wherein the crystalline magnetic layer includes at least one of Fe, Co, FeCo, or any alloy thereof. 9. The magnetic memory device of claim 7 , wherein the crystalline magnetic layer has a thickness of about 4 Å to about 5Å. 10. A magnetic memory device comprising: a bit line disposed on a substrate; a MTJ structure disposed between the bit line and the substrate, the MTJ structure including: a first reference magnetic layer; a second reference magnetic layer; a free layer disposed between the first reference magnetic layer and the second reference magnetic layer; a first tunnel barrier layer between the first reference magnetic layer and the free layer; and a second tunnel barrier layer between the second reference magnetic layer and the free layer, the second tunnel barrier layer thinner than the first tunnel barrier layer, wherein the first tunnel barrier layer is disposed at a first height from a top surface of the substrate, wherein the second tunnel barrier layer is disposed at a second height greater than the first height from the top surface of the substrate, and wherein the bit line is disposed at a third height greater than the second height from the top surface of the substrate, wherein the second tunnel barrier layer is closer to the bit line than to the substrate, and the first tunnel barrier layer is further away from the bit line than the second tunnel barrier layer. 11. The magnetic memory device of claim 10 , wherein the first and second tunnel barrier layers are formed of magnesium oxide (MgO). 12. The magnetic memory device of claim 10 , the first reference magnetic layer is in direct contact with a bottom surface of the first tunnel barrier layer and has the L 1 1 crystal structure. 13. The magnetic memory device of claim 10 , wherein a top surface of the first reference magnetic layer is in direct contact with a bottom surface of the first tunnel barrier layer and has a mean surface roughness of about 2 Å or less. 14. A magnetic memory device comprising: a first tunnel barrier layer disposed at a first height from a substrate; a second tunnel barrier layer disposed at a second height greater than the first height from the substrate, the second tunnel barrier layer thinner than the first tunnel barrier layer; a free layer disposed between the first tunnel barrier layer and the second tunnel barrier layer; a first reference magnetic layer disposed under the first tunnel barrier layer; and a second reference magnetic layer disposed over the second tunnel barrier layer, wherein the first reference magnetic layer, the second reference magnetic layer, and the free layer each have a magnetization direction substantially perpendicular to a top surface of the substrate, wherein the first and second tunnel barrier layers are formed of magnesium oxide (MgO) having a (001) crystal plane substantially parallel to a top surface of the substrate.
Cell access · CPC title
details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title
Electricity · mapped topic
Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title
using multiple magnetic layers (G11C11/155 takes precedence) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.