High-frequency semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9276104-B2
Application number	US-201314368728-A
Country	US
Kind code	B2
Filing date	Jan 30, 2013
Priority date	Feb 8, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A high-frequency semiconductor device, wherein on one surface of a semiconductor substrate, a first insulating layer, an undoped epitaxial polysilicon layer in a state of column crystal, a second insulating layer, and a semiconductor layer are formed in order from a side of the one surface, and a high-frequency transistor is formed in a location of the semiconductor layer facing the undoped epitaxial polysilicon layer with the second insulating layer in between.

First claim

The invention claimed is:

1. A high-frequency semiconductor device, comprising:
a first insulating layer;
an undoped epitaxial polysilicon layer in a state of column crystal, wherein the state of column crystal is obtained at a temperature of equal to or higher than 1000 deg C.;
a second insulating layer;
a semiconductor layer; and
a high-frequency transistor,
wherein the first insulating layer, the undoped epitaxial polysilicon layer, the second insulating layer, and the semiconductor layer are formed on one surface of a semiconductor substrate in order from the one surface, and
the high-frequency transistor is formed in a location of the semiconductor layer facing the undoped epitaxial polysilicon layer with the second insulating layer in between.

2. The high-frequency semiconductor device according to claim 1 , further comprising:
a doped epitaxial polysilicon layer formed between the first insulating layer and the undoped epitaxial polysilicon layer in the state of column crystal, the doped epitaxial polysilicon layer being interposed between the semiconductor substrate and the high-frequency transistor, and having a resistance lowered by doping with an impurity; and
a connection structure that connects the doped epitaxial polysilicon layer to a ground electric potential.

3. The high-frequency semiconductor device according to claim 2 , further comprising a first interlayer insulating film and a first wiring layer including a ground electrode layer that are laminated on a side opposite to the second insulating layer with respect to the semiconductor layer,
wherein the ground electrode layer is electrically connected to the doped epitaxial polysilicon layer through a contact plug.

4. The high-frequency semiconductor device according to claim 1 , further comprising a thermal bonding member,
wherein a heat release hole is formed, the heat release hole starting from the semiconductor substrate, passing through the first insulating layer and the doped epitaxial polysilicon layer to reach the undoped epitaxial polysilicon layer, and
the thermal bonding member is formed on an internal wall of the heat release hole, and has a higher thermal conductivity than a thermal conductivity of the first insulating layer.

5. The high-frequency semiconductor device according to claim 1 , further comprising a dummy wiring section for heat transfer to release heat generated in the high-frequency transistor through a multilayer wiring layer of the semiconductor substrate, the dummy wiring section being formed with the use of a second wiring layer on a first wiring layer in the multilayer wiring layer, and the dummy wiring section not connecting to an other electrically-conductive member used as a wiring of a circuit or an element.

6. The high-frequency semiconductor device according to claim 1 , further comprising:
an insulating support substrate bonded to a surface of the semiconductor substrate on which a multilayer wiring layer is formed; and
a passive element formed on the support substrate.

7. The high-frequency semiconductor device according to claim 1 , wherein the high-frequency transistor is an antenna switch element.

8. The high-frequency semiconductor device according to claim 1 , wherein a thickness of the undoped epitaxial polysilicon layer in the state of column crystal is equal to or larger than 45 μm, and a thickness of the second insulating layer is from 0.1 μm to 0.5 μm both inclusive.

9. A method of manufacturing a high-frequency semiconductor device, the method comprising:
laminating a first insulating layer, a doped epitaxial polysilicon layer having a resistance lowered by doping with an impurity, an undoped epitaxial polysilicon layer in a state of column crystal, a second insulating layer, and a semiconductor layer in this order on a semiconductor substrate;
forming a high-frequency transistor including a channel region in the semiconductor layer;
forming an electrode layer in a first multilayer wiring layer of the semiconductor substrate, the electrode layer being connected to the high-frequency transistor with a contact plug in between; and
forming a ground connection structure that connects the doped epitaxial polysilicon layer to a ground electric potential; wherein out of the doped epitaxial polysilicon layer and the undoped epitaxial polysilicon layer in the state of column crystal, at least the undoped epitaxial polysilicon layer in the state of column crystal is formed at a temperature equal to or higher than 1000 deg C with the use of an epitaxial growth technology.

10. The method according to claim 9 , wherein, in forming the ground connection structure of the ground electric potential,
a first contact plug is formed, the first contact plug starting from a region other than the channel region to reach the doped epitaxial polysilicon layer, and
upon forming the contact plug and the electrode layer with respect to the high-frequency transistor, a second contact plug and a ground electrode layer are formed, the second contact plug being connected to the first contact plug, and the ground electrode layer being connected to the second contact plug.

11. The method according to claim 9 , wherein
the semiconductor substrate is bonded to a support substrate from a side of a surface on which the multilayer wiring layer is formed,
the semiconductor substrate is thinned from a rear surface of the semiconductor substrate after the bonding to the support substrate,
a heat release hole is formed, the heat release hole starting from a rear surface of the thinned semiconductor substrate to reach the doped epitaxial polysilicon layer, and
a thermal bonding member is formed on a side wall in the formed heat release hole, the thermal bonding member having a higher thermal conductivity then a thermal conductivity of the first insulating layer, and the thermal bonding member being in contact with the doped epitaxial polysilicon layer, the undoped epitaxial polysilicon layer in the state of column crystal, and the semiconductor substrate.

12. The method according to claim 11 , wherein
the heat release hole is formed so that a side wall is in a forward tapered shape,
a connection hole for leading out a wiring to an external terminal side is formed from the rear surface of the thinned semiconductor substrate to the multilayer wiring layer so that a side wall is in a reverse tapered shape,
an insulating film is formed on internal side walls of the heat release hole and the connection hole, and anisotropic etching is performed so that the insulating film is removed from the side wall of the heat release hole in the forward tapered shape and is left on the side wall of the connection hole in the reverse tapered shape, and
an electrically-conductive film and a connection film are concurrently formed, the electrically-conductive film being as the thermal bonding member provided on the side wall of the heat release hole after removing the insulating film, and the connection film passing from an internal bottom surface of the connection hole and the insulating film left on the side wall of the connection hole in the reverse tapered shape to reach the rear surface of the semiconductor substrate.

13. The method according to claim 9 , wherein in the multilayer wiring layer, a dummy wiring section is formed for heat transfer to release heat generated in the high-frequency transistor through the multilayer wiring layer, the dummy wiring section not connecting to an other electrically-conductive member used as a wiring of a circuit or an element.

14. The method according to claim 9 , wherein
the high-frequency transistor and

Assignees

• Sony Corp

Inventors

• TSUNEMI Hiroki
• Yamagata Hideo
• Nagai Kenji
• Ibusuki Yuji

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title