Semiconductor device

Patent metadata

Field	Value
Publication number	US-9276094-B2
Application number	US-201414472154-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Nov 13, 2008
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layer;
a power device including a first gate electrode, a second gate electrode, an emitter electrode, and a collector electrode, said first and second gate electrodes and said emitter electrode being formed on a top surface of said semiconductor layer, said collector electrode being formed on a bottom surface of said semiconductor layer;
a gate wire for supplying a gate drive signal to said first gate electrode; and
supply means for supplying said gate drive signal to said second gate electrode when said gate drive signal is at a high level and a voltage on said semiconductor layer is at a low level.

2. The semiconductor device as claimed in claim 1 , wherein said supply means includes:
a NOT circuit connected to said gate wire; and
a NOR circuit for performing a NOR operation on the output of said NOT circuit and said voltage on said semiconductor layer and outputting the result to said second gate electrode.

3. A semiconductor device comprising:
a semiconductor layer;
a power device including a first gate electrode, a second gate electrode, an emitter electrode, and a collector electrode, said first and second gate electrodes and said emitter electrode being formed on a top surface of said semiconductor layer, said collector electrode being formed on a bottom surface of said semiconductor layer;
a gate wire configured to supply a gate drive signal to said first gate electrode; and
a supply circuit connected to said second gate electrode and configured to supply said gate drive signal to said second gate electrode when said gate drive signal is at a high level and a voltage on said semiconductor layer is at a low level.

4. The semiconductor device as claimed in claim 3 , wherein said supply circuit includes:
a NOT circuit connected to said gate wire; and
a NOR circuit configured to perform a NOR operation on the output of said NOT circuit and said voltage on said semiconductor layer and configured to output the result of said NOR operation to said second gate electrode.

Assignees

• Mitsubishi Electric Corp

Inventors

• Kusunoki Shigeru

Classifications

• H03K17/08

  Modifications for protecting switching circuit against overcurrent or overvoltage · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D62/112

  for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers · CPC title

• H10D84/854

  comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention · CPC title

• H10D84/0188 Primary

  Manufacturing their isolation regions · CPC title