Semiconductor structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9276085-B2
Application number	US-201214387143-A
Country	US
Kind code	B2
Filing date	Apr 26, 2012
Priority date	Mar 23, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

First claim

We claim:

1. A method for manufacturing a semiconductor structure, comprising
a) providing a substrate ( 100 ) and forming a gate stack on the substrate ( 100 )
b) forming an offset spacer ( 220 ) around the gate stack and a dummy spacer ( 230 ) around the offset spacer ( 220 );
c) forming a doped region ( 330 a ) in the substrate ( 100 ) on both sides of the offset spacer ( 220 ) and the dummy spacer ( 230 )
d) removing the dummy spacer ( 230 ), and a lower portion of the offset spacer ( 220 ) entirely located on the surface of the substrate ( 100 ) up to a gate dielectric layer ( 200 ); and
e) etching the substrate ( 100 ) on both sides of the offset spacer ( 220 ) to form a trench ( 360 )
f) forming a source/drain junction extension ( 310 ) in the trench ( 360 )
g) forming a spacer ( 240 ) on sidewalls of the offset spacer ( 220 ); and
h) forming a source/drain region ( 330 ) in the substrate ( 100 ) on both sides of the spacer ( 240 ).

2. The method according to claim 1 , wherein the step c) comprises:
etching the substrate ( 100 ) with the gate stack having the offset spacer ( 220 ) and the dummy spacer ( 230 ) as a mask to form a trench ( 350 ) on both sides of the gate stack; and
forming a doped region ( 330 a ) in the trench ( 350 ) by means of epitaxial growth with the substrate ( 100 ) as a seed crystal.

3. The method according to claim 1 , wherein the step f) comprises:
filling the trench ( 360 ) by means of epitaxial growth with the substrate ( 100 ) as a seed crystal, and simultaneously performing in-situ doping to form a source/drain junction extension ( 310 ).

4. The method according to claim 1 , wherein the material of the source/drain junction extension ( 310 ) and/or the source/drain region ( 330 ) is an alloy of the substrate material.

5. The method according to claim 4 , wherein:
for N-type devices, the lattice constant of the material of the source/drain junction extension ( 310 ) and/or the source/drain region ( 330 ) is less than or equal to that of the material of the substrate ( 100 ); and
for P-type devices, the lattice constant of the material of the source/drain junction extension ( 310 ) and/or the source/drain region ( 330 ) is greater than or equal to that of the material of the substrate ( 100 ).

6. The method according to claim 1 , wherein the junction depth of the source/drain junction extension ( 310 ) is in the range of 3 nm to 50 nm, and the doping concentration is from 5×10 18 cm −3 to 5×10 20 cm −3 .

7. The method according to claim 1 , wherein the step h) comprises:
forming a source/drain region ( 330 ) by ion implantation to the substrate ( 100 ) on both sides of the spacer ( 240 ).

8. The method according to claim 1 , wherein the gate stack comprises a gate dielectric layer ( 200 ) and a dummy gate ( 210 ).

Assignees

• Yin Huaxiang
• Ma Xiaolong
• Qi Changliang
• Xu Qiuxia
• Chen Dapeng
• Inst Of Microelectronics Cas

Inventors

• Yin Huaxiang
• Ma Xiaolong
• Qi Changliang
• Xu Qiuxia
• Chen Dapeng

Classifications

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/015

  removing at least parts of gate spacers, e.g. disposable spacers · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D62/021 Primary

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title