Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9275940-B2
Application number	US-201414328527-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Jul 19, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A semiconductor device is provided which complies with restrictions on layout on a mounting substrate side. The semiconductor device includes a wiring substrate having a plurality of bonding leads at an upper surface having a rectangular shape, a semiconductor chip mounted over the upper surface of the wiring substrate, and having a plurality of electrode pads at a main surface having a rectangular shape similar to a square shape, and a plurality of metal wires for coupling the bonding leads of the wiring substrate to the electrode pads of the semiconductor chip. In a BGA, the metal wires are arranged at three sides of a main surface of the semiconductor chip, the bonding leads are provided in lines at the upper surface of the wiring substrate outside the respective opposed short sides of the main surface of the semiconductor chip, and the metal wires are coupled to the bonding leads.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a wiring substrate having a first surface and a second surface opposite thereto, the first surface being formed in a rectangular shape and provided with a plurality of leads;
a semiconductor chip having a quadrilateral main surface and a back surface opposite thereto, the main surface being provided with a plurality of electrode pads, the semiconductor chip being mounted over the first surface of the wiring substrate;
a plurality of metal wires for electrically coupling the leads of the wiring substrate to the electrode pads of the semiconductor chip; and
a plurality of terminals for external coupling provided at the second surface of the wiring substrate,
wherein the metal wires are respectively arranged at three out of four sides of the main surface of the semiconductor chip,
wherein the leads are provided in:
a plurality of lines at the first surface of the wiring substrate along a short side of the first surface outside the respective sides of any one of two pairs of the opposed sides of the main surface of the semiconductor chip; and
a line formed along a long side of the first surface, a distance between the short side of the first surface and the plurality of lines being greater than a distance between the long side of the first surface and the line formed along the long side of the first surface, and

wherein the metal wires are electrically coupled to the leads.

2. The semiconductor device according to claim 1 , wherein the metal wires arranged in parallel along the short side of the first surface of the wiring substrate are arranged at two opposed sides of the main surface of the semiconductor chip,
wherein the leads are provided in lines along the short side of the first surface outside the two opposed sides of the chip, and
wherein the metal wires are electrically coupled to the leads.

3. The semiconductor device according to claim 2 , wherein the metal wires are arranged at one side intersecting the two opposed sides of the main surface of the semiconductor chip,
wherein the line formed along a long side of the first surface comprises leads which are arranged in one line outside the intersecting one side at the first surface of the wiring substrate, and
wherein the metal wires are electrically coupled to the leads.

4. The semiconductor device according to claim 2 , wherein the leads are provided in three lines along the short side of the first surface outside one of the two opposed sides of the chip.

5. The semiconductor device according to claim 2 , wherein the leads are provided in two lines along the short side of the first surface outside the other side of the two opposed sides of the chip.

6. The semiconductor device according to claim 2 , wherein the line formed along a long side of the first surface comprises leads which are are provided in one line along the long side of the first surface outside one side intersecting the two opposed sides of the chip.

7. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a memory circuit and a logic circuit.

8. The semiconductor device according to claim 1 , wherein the main surface of the semiconductor chip is formed in a rectangle shape, and
wherein two opposed long sides of the main surface of the rectangle shape are arranged to extend along the respective long sides of the first surface of the wiring substrate.

9. The semiconductor device according to claim 8 , wherein the leads are provided in a plurality of lines at the first surface of the wiring substrate outside the respective opposed short sides of the main surface of the semiconductor chip along the respective short sides, and
wherein the metal wires are electrically coupled to the leads formed in the lines.

10. The semiconductor device according to claim 8 , wherein a plurality of first electrode pads are formed at the main surface along the side not having the metal wires disposed thereat among the sides of the rectangle main surface of the semiconductor chip; and
wherein the metal wire is not coupled to any one of the first electrode pads.

11. The semiconductor device according to claim 10 , wherein the first electrode pads are electrically coupled to a protective circuit formed in the semiconductor chip.

12. The semiconductor device according to claim 8 , wherein a plurality of respective electrode pads formed at the main surface of the semiconductor chip along the two opposed short sides of the main surface of the semiconductor chip is provided in a staggered arrangement.

13. The semiconductor device according to claim 8 , further comprising:
a wiring pattern formed on the first surface of the wiring substrate,
wherein the wiring pattern is not formed beside one of the two opposed long sides of the main surface of the semiconductor chip with the metal wires disposed thereat and outside the line formed along the long side of the first surface of the wiring substrate.

14. The semiconductor device according to claim 1 , wherein a seal body is formed over the first surface of the wiring substrate to seal the semiconductor chip and the metal wires therewith.

15. The semiconductor device according to claim 1 , further comprising:
a wiring pattern formed on the first surface,
wherein the semiconductor chip is formed in a chip mounting region on the first surface of the wiring substrate, and the wiring pattern comprises a wiring portion extending from the line formed along the long side of the first surface, into the chip mounting region.

16. The semiconductor device according to claim 15 , further comprising:
through hole wirings formed in the wiring substrate in the chip mounting region,
wherein the leads formed in the line formed along a long side of the first surface are electrically coupled to the plurality of terminals via the through hole wirings.

Assignees

• Renesas Electronics Corp

Inventors

• Ohashi Akira
• Umezu Akira
• Takeda Hiromitsu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title