Method of manufacturing a junction electronic device having a 2-dimensional material as a channel

Patent metadata

Field	Value
Publication number	US-9275860-B2
Application number	US-201414258416-A
Country	US
Kind code	B2
Filing date	Apr 22, 2014
Priority date	Feb 10, 2014
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A method of manufacturing a junction electronic device having a 2-Dimensional (2D) material as a channel, includes forming a pattern portion by surface-treating a substrate so that the patterned portion has a higher surface potential than other portions of the substrate; bonding a 2D material to rthe patterned portion having the higher surface potential by spraying a liquid including 2D material flakes onto the substrate; forming a pair of first electrodes in contact with both ends of the 2D material disposed on the substrate; forming a dielectric layer on the first electrodes and the 2D material; and forming a second electrode on the dielectric layer. The 2D materials are disposed at desired positions by chemical exfoliation.

First claim

What is claimed is:

1. A method of manufacturing a junction electronic device having a 2-Dimensional (2D) material as a channel, comprising:
forming a patterned portion by surface-treating a substrate so that the patterned portion has a higher surface potential than other portions of the substrate;
bonding a 2D material to the patterned portion having the higher surface potential by spraying a liquid including 2D material flakes onto the substrate;
forming a pair of first electrodes in contact with both ends of the 2D material disposed on the substrate;
forming a dielectric layer on the first electrodes and the 2D material; and
forming a second electrode on the dielectric layer.

2. The method of claim 1 , wherein the substrate is selected from the group consisting of a silicon substrate, a silicon oxide substrate, and a plastic substrate.

3. The method of claim 1 , wherein the 2D material is selected from the group consisting of MoS 2 , WS 2 , MoSe 2 , and WSe 2 , and the liquid is a mixture of ethanol and water.

4. The method of claim 1 , wherein the surface-treating of the substrate includes forming nano sized portions by using mechanical lithography using an Atomic Force Microscope (AFM).

5. The method of claim 1 , wherein the first and second electrodes are made of metal or graphene.

6. The method of claim 1 , wherein the dielectric layer is formed of one or more materials selected from the group consisting of HfO 2 , AlO 3 , and SiO 2 .

Assignees

• Korea Electronics Telecomm

Inventors

• Yu Young Jun
• Kim Jin Soo
• Choi Hong Kyw
• Choi Jin Sik
• Kim Jin Tae
• Chung Kwang Hyo
• Youn Doo Hyeb
• Choi Choon Gi

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/2922

  being non-crystalline insulating materials, e.g. glass or polymers · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/265 Primary

  using solutions · CPC title