Utilizing destructive features as RAM code for a storage device

US9275697B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9275697-B2
Application numberUS-201314088739-A
CountryUS
Kind codeB2
Filing dateNov 25, 2013
Priority dateOct 3, 2013
Publication dateMar 1, 2016
Grant dateMar 1, 2016

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A host including a controller configured to be connected to a storage device separate from the host. The controller is configured to maintain random access memory (RAM) code on the host, the RAM code configured to provide a destructive function, temporarily load the RAM code onto a volatile memory in the storage device during a manufacturing process, wherein the loaded RAM code, when executed by a processor in the storage device, is configured to cause the processor in the storage device to perform a destructive function on the storage device, and remove the loaded RAM code from the volatile memory after the manufacturing process, wherein the destructive function is unable to be performed by the processor when the loaded RAM code is removed from the volatile memory.

First claim

Opening claim text (preview).

What is claimed is: 1. A host computing device comprising: a controller configured to be connected to a data storage device separate from the host computing device and to: maintain random access memory (RAM) code on the host device, the RAM code including instructions for performing a destructive function on the data storage device; temporarily load the RAM code onto a volatile memory of the data storage device during a manufacturing process, wherein the loaded RAM code, when e…

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What does patent US9275697B2 cover?
A host including a controller configured to be connected to a storage device separate from the host. The controller is configured to maintain random access memory (RAM) code on the host, the RAM code configured to provide a destructive function, temporarily load the RAM code onto a volatile memory in the storage device during a manufacturing process, wherein the loaded RAM code, when executed b…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification B62D31/006. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).