Energy conservation in a multicore chip

Patent metadata

Field	Value
Publication number	US-9275696-B2
Application number	US-201213812967-A
Country	US
Kind code	B2
Filing date	Jul 26, 2012
Priority date	Jul 26, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

Technologies are described herein for conserving energy in a multicore chip via selectively refreshing memory directory entries. Some described examples may refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip. More particularly, a directory entry may be accessed in the cache coherence directory stored in the DRAM. Some further examples may identify a cache coherence state of a block associated with the directory entry. In some examples, refresh of the directory entry stored in the DRAM may be selectively disabled based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

First claim

What is claimed is:

1. A method to refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip, the method comprising:
accessing a directory entry in the cache coherence directory stored in the DRAM, the directory entry comprising a sharers item that identifies which of a plurality of cache memories in the multicore chip store a block associated with the directory entry, and an error correction code (ECC) for either or both detection and correction of an error in the sharers item;
detecting the error in the sharers item based on the ECC;
in response to a determination that the detected error is not correctable by use of the ECC:
broadcasting a message to each cache memory of the plurality of cache memories in the multicore chip, wherein the message requests each cache memory to determine if the corresponding cache memory contains the block;
receiving replies to the message; and
updating the sharers item to correct the detected error based on the received replies;

identifying the cache coherence state of the block associated with the directory entry; and
selectively disabling a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

2. The method of claim 1 , wherein selectively disabling further comprises disabling the refresh of the directory entry when the cache coherence state is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

3. The method of claim 1 , further comprising selectively enabling the refresh of the directory entry when the cache coherence state is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

4. The method of claim 1 , further comprising selectively enabling the refresh of the directory entry when the cache coherence state is identified as a shared state.

5. The method of claim 1 , further comprising:
when the cache coherence state of the block is identified as a shared state:
identifying a last time when the block was accessed;
calculating a difference between a current time and the last time; determining if the difference exceeds a threshold;
disabling refresh of the directory entry when the difference exceeds the threshold; and
enabling refresh of the directory entry when the difference does not exceed the threshold.

6. The method of claim 1 , wherein the directory entry
further comprises a tag identifying the block and the cache coherence state of the block.

7. The method of claim 6 , further comprising:
determining whether the detected error is correctable using the ECC; and
correcting the detected error using the ECC when the detected error is correctable.

8. The method of claim 1 , wherein detecting the error in the sharers item based on the ECC comprises:
reading the sharers item and the ECC in the directory entry;
computing a new ECC based on the sharers item; and
detecting the error in the sharers item when the new ECC does not match the ECC in the directory entry.

9. The method of claim 7 , wherein accessing the directory entry comprising the sharers item identifying which of the plurality of cache memories in the multicore chip store the block comprises:
accessing the sharers item comprising a bit vector, the bit vector comprising a plurality of bits, wherein each of the plurality of bits in the bit vector is associated with one or more cache memories of the plurality of cache memories in the multicore chip.

10. The method of claim 8 , wherein detecting the error in the sharers item when the new ECC does not match the ECC in the directory entry comprises:
detecting up to a two-bit error in the bit vector and correcting a one-bit error in the bit vector using the ECC, the ECC comprising a 1-error-correction, 2-error-detection (1EC2ED) code.

11. The method of claim 10 , further comprising:
detecting a greater than two-bit error in the bit vector using an additional error direction code contained in the directory entry.

12. A non-transitory computer-readable storage medium having computer-executable instructions stored thereon which, in response to execution by a computing device, cause the computing device to:
access a directory entry in a cache coherence directory of a multicore chip stored in a dynamic random access memory (DRAM), the directory entry comprising a sharers item that identifies which of a plurality of cache memories in the multicore chip store a block associated with the directory entry, and an error correction code (ECC) for either or both detection and correction of an error in the sharers item;
detect the error in the sharers item based on the ECC;
in response to a determination that the detected error is not correctable by use of the ECC:
broadcast a message to each cache memory of the plurality of cache memories in the multicore chip, wherein the message requests each cache memory to determine if the corresponding cache memory contains the block;
receive replies to the message; and
update the sharers item to correct the detected error based on the received replies;

identify the cache coherence state of the block associated with the directory entry; and
selectively disable a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the computer-executable instructions, in response to execution by the computing device, further cause the computing device to:
selectively disable the refresh of the directory entry stored in the DRAM when the cache coherence state of the block is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

14. The non-transitory computer-readable storage medium of claim 12 , wherein the computer-executable instructions, in response to execution by the computing device, further cause the computing device to:
selectively enable the refresh of the directory entry stored in the DRAM when the cache coherence state of the block is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

15. The non-transitory computer-readable storage medium of claim 12 , wherein the computer-executable instructions, in response to execution by the computing device, further because the computing device to:
selectively enable the refresh of the directory entry stored in the DRAM when the cache coherence state is identified as a shared state.

16. The non-transitory computer-readable storage medium of claim 12 , wherein the computer-executable instructions, in response to execution by the computing device, further cause the computing device to:
when the cache coherence state of the block is identified as a shared state:
identify a last time when the block was last accessed;
calculate a difference between a current time and the last time; determine if the difference exceeds a threshold;
disable the refresh of the directory entry stored in the DRAM when the difference is determined to exceed the threshold; and
enable the refresh of the directory entry stored in the DRAM when the difference is determined not to exceed the threshold.

17. The non-transitory computer-readable storage medium of claim 12 , wherein to refresh the directory entry, the computer-executable instru

Assignees

• Solihin Yan
• Empire Technology Dev Llc

Inventors

• Solihin Yan

Classifications

• G11C11/40622 Primary

  Partial refresh of memory arrays · CPC title

• G06F12/0817

  using directory methods · CPC title

• G06F2212/403

  Error protection encoding, e.g. using parity or ECC codes · CPC title

• G06F12/0813

  with a network or matrix configuration · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title