Gate drive circuit, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-9275589-B2
Application number	US-201314143423-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Jan 23, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A gate drive circuit, comprising: a plurality of shift register units each having a signal output end, wherein the signal output end of one of the plurality of shift register units except the last one is connected to the signal input end of the next one; L arithmetic units each having a plurality of input ends, wherein L is an integer equal to or larger than 2, and one of the plurality of input ends of each of the L arithmetic units is connected to the signal output end of a respective shift register unit; and a clock generation unit having a plurality of clock output ends for outputting different clock signals, wherein at least one of the plurality of clock output ends is connected to at least one of the other input ends of a respective arithmetic unit except the one input end connected to the signal output end of the shift register unit, so that the L arithmetic units output L different drive signals.

First claim

What is claimed is:

1. A gate drive circuit, comprising:
a plurality of shift register units each having a signal output end, wherein the signal output end of one of the plurality of shift register units except the last one is connected to the signal input end of the next one;
L arithmetic units each having a plurality of input ends, wherein L is an integer equal to or larger than 2, and one of the plurality of input ends of each of the L arithmetic units is connected to the signal output end of a respective shift register unit; and
a clock generation unit having a plurality of clock output ends for outputting different clock signals, wherein at least one of the plurality of clock output ends is connected to at least one of the other input ends of a respective arithmetic unit except the one input end connected to the signal output end of the shift register unit, so that the L arithmetic units output L different drive signals,
wherein the clock generation unit comprising:
a sub clock generation unit configured to generate m different first clock signals and output the m first clock signals through m first clock output ends of the plurality of clock output ends, wherein m is an integer equal to or larger than 1 and less than L; and
a sub shift register unit connected to the sub clock generation unit and configured to shift the m first clock signals generated by the sub clock generation unit so as to generate (L−m) different second clock signals and output the (L−m) different second clock signals through (L−m) second clock output ends of the plurality of clock output ends,

wherein at least one of the first clock output ends and the second clock output ends is connected to the at least one of the other input ends of each of the L arithmetic unit, so that L clock output ends of the clock generation unit consist of first clock output ends of the sub clock generation unit and second clock output ends of the sub shift register unit.

2. The gate drive circuit according to claim 1 ,
wherein each of the L arithmetic units comprising:
a NAND gate having two input ends; and
a NOT gate connected to the NAND gate in series.

3. The gate drive circuit according to claim 1 ,
wherein each of the L arithmetic units comprising:
a NAND gate having three input ends; and
a NOT gate connected to the NAND gate in series.

4. The gate drive circuit according to claim 1 ,
wherein the output end of each of the L arithmetic units is connected with an output buffer unit.

5. The gate drive circuit according to claim 4 ,
wherein each of the output buffer units comprises an even number of inverters connected in series.

6. The gate drive circuit according to claim 1 , wherein L is 2 or 4.

7. The gate drive circuit according to claim 2 ,
wherein the clock signals each has a pulse width equal to 1/L of a pulse width of a signal output from the signal output end of the shift register unit; and
wherein the clock signals each has a period equal to the pulse width of the signal output from the signal output end of the shift register unit.

8. An array substrate, comprising:
a plurality of gate lines and a plurality of data lines;
a plurality of thin film transistors formed in a plurality of pixel regions defined by the plurality of gate lines and the plurality of data lines, respectively; and
a gate drive circuit according to claim 1 , configured to provide a drive signal for the gate lines.

9. The array substrate according to claim 8 ,
wherein each of the L arithmetic units comprising:
a NAND gate having two input ends; and
a NOT gate connected to the NAND gate in series.

10. The array substrate according to claim 8 ,
wherein each of the L arithmetic units comprising:
a NAND gate having three input ends; and
a NOT gate connected to the NAND gate in series.

11. The array substrate according to claim 8 ,
wherein the output end of each of the L arithmetic units is connected with an output buffer unit.

12. The array substrate according to claim 11 ,
wherein each of the output buffer units comprises an even number of inverters connected in series.

13. The array substrate according to claim 8 , wherein L is 2 or 4.

14. The array substrate according to claim 9 ,
wherein the clock signals each has a pulse width equal to 1/L of a pulse width of a signal output from the signal output end of the shift register unit; and
wherein the clock signals each has a period equal to the pulse width of the signal output from the signal output end of the shift register unit.

15. A display apparatus, comprising an array substrate according to claim 8 .

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Hu Like
• Qi Xiaojing

Classifications

• G09G3/3655 Primary

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title