Interface device and method for consistently exchanging data

Patent metadata

Field	Value
Publication number	US-9274993-B2
Application number	US-201313847861-A
Country	US
Kind code	B2
Filing date	Mar 20, 2013
Priority date	Mar 23, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

An interface device for exchanging data between a first bus system and a second bus system, wherein an input/output device is connectable to the second bus system and within the input/output device includes an addressable slot and an addressable subslot for output or acceptance of input/output data to optimize the consistent exchange of the data between the bus systems. A data transfer device including a transfer memory is connected via the control device and a list storage device in which a data structure for addressing the data for the input/output device is stored, and wherein the data structure is predetermined for a plurality of subslots in a telegram format of the telegrams of the first bus system.

First claim

What is claimed is:

1. An interface device for exchange of data between a first bus system and a second bus system, wherein an input/output device is connectable to the second bus system and the input/output device includes an addressable slot and an addressable subslot for outputting or accepting input/output data, the interface device comprising:
a first transceiver device for data of the first bus system;
a second transceiver device for data of the second bus system;
a data transfer device including a transfer memory;
a controller configured to control data storage and to coordinate write accesses in the data transfer device or at the data transfer device;
a list storage device connected to the controller, the list storage device storing a data structure for addressing data for the input/output device, the data structure being predetermined for a plurality of subslots in a telegram format of telegrams of the first bus system, the list storage device including a memory offset related to a start address of the transfer memory and a data length of the input/output data, and each of the plurality of subslots in the data structure being assigned an index;
wherein the control device is further configured to update the input/output data aided with by the index to coordinate the write accesses in the data transfer device byte-by-byte;
wherein the transfer memory comprises a first transfer memory and a second transfer memory, the first and second transfer memories being connected to the control device such that a storage of data or a write access is implemented one of only to the first transfer memory and only to the second transfer memory;
wherein the control device includes a blocking device configured to set the status indicator before a write access with output data to the output buffer or before a read access of input data to the input buffer; and
wherein the control device is further configured such that the blocking device blocks a switch between the first transfer memory and the second transfer memory when the status indicator is set.

2. The interface device as claimed in claim 1 , wherein the transfer memory is divided up into an output buffer configured to buffer data from the first bus system and to provide said buffered data to the second bus system as output data for the input/output device and into an input buffer; and wherein the output buffer configured to buffer data from the second bus system and to provide the buffered data to the first bus system as input data of the input/output device.

3. The interface device as claimed in claim 1 , wherein the interface device is configured to operate in a network of an industrial automation system; wherein the first transceiver device is configured for data of the first bus system to sending and receive data of a field bus of industrial automation technology and the second transceiver device is configured for data of the second bus system to send and receive data of a backplane bus of the input output device equipped as a decentralized peripheral of the industrial automation technology, the control device further include a backplane bus controller and a field bus controller.

4. A method for consistent data exchange between a first bus system and a second bus system, the method comprising the steps of:
connecting an input/output device to the second bus system;
addressing a slot and a subslot within the input/output device to output or accept input/output data;
operating a first transceiver device to send and receive data of the first bus system;
operating a second transceiver device to send and receive data for the second bus system;
controlling a data transfer device including a transfer memory via a control device to control data storage and to coordinate write accesses into the data transfer device or at the data transfer device;
evaluting, by the control device, a data structure from a list storage device, the data structure for addressing the data for the input output device being stored before a beginning of the data exchange in the list storage device and the data structure being defined based on a plurality of sub slots in a telegram format of telegrams of the first bus system, and the list storage device including a memory offset related to a start address of the transfer memory and data lengths of the input output data, and each of the plurality of subslots in the data structure being assigned an index;
operating a blocking device in the control device;
setting a status indicator; and
blocking a switch between the first and the second transfer memory with the set status indicator before one of a write access with output data to the output buffer and before a read access of input data to the input buffer;
wherein the control device, for an updating of the input/output data, coordinates the write accesses into the data transfer device byte-by-byte with the aid of the index.

5. The interface device as claimed in claim 2 , wherein the control device is further configured to interrogate a semaphore and depending on a state of the semaphore read out output data from one of the first transfer memory and the second transfer memory for a read access of output data from the output buffer.

6. The interface device as claimed in claim 5 , wherein the transfer memory is structured byte-by-byte and each byte is assigned a semaphore with the index; wherein a byte in the first transfer memory is assigned the semaphore with a first state and a corresponding byte in the second transfer memory is assigned a semaphore with a second state; and wherein the second state corresponds to the negated first state.

7. The interface device as claimed in claim 1 , wherein the list storage device comprises a first list storage device and a second list storage device.

8. The method as claimed in 4 , wherein the transfer memory is divided into an output buffer and an input buffer; the method further comprising the steps of:
operating the output buffer to buffer data from the first bus system and provide the buffered data to the second bus system as output data for the input/output device; and
operating the input buffer to buffer data from the second bus system and to provide the buffered data to the first bus system as input data of the input/output device.

9. The method as claimed in claim 4 , wherein the transfer memory is divided up into a first transfer memory and a second transfer memory, wherein the controls a data storage or a write access such that one of only access to the first transfer memory and only access to the second transfer memory occurs.

10. The method as claimed in claim 4 ; wherein the list storage device is maintained as a duplicated list and a first list storage device and a second list storage device are created.

11. The method as claimed in claim 4 , further comprising the steps of:
implementing the method in a network or industrial automation system;
operating the first transceiver device is operated for data of a field bus of industrial automation technology;
operating the second transceiver device for data of a backplane bus of the input/output device which is configured as a decentralized peripheral of industrial automation technology; and
operating a backplane bus controller and a field bus controller in the control unit.

12. The method as claimed in claim 8 , wherein the transfer memory is divided up into a first transfer memory and a second transfer memory, wherein the controls a data storage or a write access such that one of only access to the first transfer memory and only access to the second transfer memory occurs.

13. A method for consistent data exchange between a first b

Assignees

• Siemens Ag

Inventors

• Beyer Hans-Jürgen
• Bodenschatz Markus
• Klug Andreas

Classifications

• G06F13/4036

  and deadlock prevention · CPC title

• G06F13/4059 Primary

  where the synchronisation uses buffers, e.g. for speed matching between buses · CPC title