Systems and methods for data processing using global iteration result reuse

Patent metadata

Field	Value
Publication number	US-9274889-B2
Application number	US-201313912059-A
Country	US
Kind code	B2
Filing date	Jun 6, 2013
Priority date	May 29, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for use of a detector output by a data decoder. As an example, a data processing system is discussed that includes a data detector circuit operable to provide a first detector output and a second detector output, and a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output. The combined detector output includes a unified data set element generated by combining an element of the first input with a corresponding element of the second input.

First claim

What is claimed is:

1. A data processing system, the data processing system comprising:
a data detector circuit operable to apply a data detection algorithm to a data input to yield a first detector output, and to reapply the data detection algorithm to the data input to yield a second detector output;
a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output, wherein the combined detector output includes a unified data set element generated by combining an element of the first input with a corresponding element of the second input;
a data decoder circuit operable to apply a data decoding algorithm to a decoder input derived from the combined detector output to yield a decoded output; and
wherein applying the data detection algorithm and applying the data decoding algorithm at least one time corresponds to a global iteration, and wherein the combining circuit is operable to combine the element of the first input with the corresponding element of the second input in a first proportion when the data decoding algorithm failed to converge and a number of global iterations is less than a threshold value and a second proportion when the data decoding algorithm failed to converge and the number of global iterations is greater than the threshold value, and wherein the first proportion is different from the second proportion.

2. The data processing system of claim 1 , wherein the decoder input is a first instance of the decoder input, and wherein reapplying the data detection algorithm to the data input to yield the second detector output is guided by a second instance of the decoder input.

3. The data processing system of claim 1 , wherein the system is implemented as an integrated circuit.

4. The data processing system of claim 1 , wherein the system is implemented as part of a device selected from a group consisting of: a communication device, and a storage device.

5. The data processing system of claim 1 , wherein the data decoder circuit is a low density parity check decoder circuit.

6. The data processing system of claim 1 , wherein the data detection algorithm is selected from a group consisting of: a Viterbi data detection algorithm, and a maximum a posterior data detection algorithm.

7. The data processing system of claim 1 , wherein the combined detector output is a first combined detector output, wherein the threshold value is a first threshold value, wherein the data detector circuit is further operable to apply the data detection algorithm to the data input to yield a third detector output, wherein the third detector output occurs coincident to the first threshold value, and wherein the combining circuit is further operable to combine the second input with a third input derived from the third detector output to yield a second combined detector output when the number of global iterations is equal to a second threshold value.

8. A method for data processing, the method comprising:
applying a data detection algorithm using a data detector circuit to a data input to yield a first detector output;
re-applying the data detection algorithm using the data detector circuit to the data input to yield a second detector output;
combining a first input derived from the first detector output with a second input derived from the second detector output in a determined proportion to yield a combined detector output, wherein the determined proportion is selected from a group consisting of:
a first proportion when a data decoding algorithm failed to converge and a number of global iterations is less than a threshold value or a second proportion when the data decoding algorithm failed to converge and the number of global iterations is greater than the threshold value; and
a first proportion when a number of unsatisfied checks remaining in a decoded output is non-zero and exceeds a threshold value, and a second proportion when the number of unsatisfied checks is non-zero and is less than the threshold value; and

applying the data decoding algorithm using a data decoder circuit to a decoder input derived from the combined detector output to yield a decoded output and the number of unsatisfied checks remaining in the decoded output, wherein applying the data detection algorithm and applying the data decoding algorithm at least one time corresponds to the global iteration.

9. The method of claim 8 , wherein the combined detector output is a first combined detector output, wherein the threshold value is a first threshold value, and wherein the method further comprises:
re-applying the data detection algorithm to the data input to yield a third detector output, wherein the third detector output occurs coincident to the first threshold value; and
combining the second input with a third input derived from the third detector output to yield a second combined detector output when the number of global iterations is equal to a second threshold value.

10. The method of claim 8 , wherein the decoder input is a first instance of the decoder input, and wherein reapplying the data detection algorithm to the data input to yield the second detector output is guided by a second instance of the decoder input.

11. The method of claim 8 , wherein the data decoder circuit is a low density parity check decoder circuit, and wherein the data detection algorithm is selected from a group consisting of: a Viterbi data detection algorithm, and a maximum a posterior data detection algorithm.

12. A data processing system, the data processing system comprising:
a data detector circuit operable to apply a data detection algorithm to a data input to yield a first detector output, and to reapply the data detection algorithm to the data input to yield a second detector output;
a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output;
a data decoder circuit operable to apply a data decoding algorithm to a decoder input derived from the combined detector output to yield a decoded output and a number of unsatisfied checks; and
wherein the combining circuit is operable to combine the first input with the second input in a first proportion when the number of unsatisfied checks is non-zero and exceeds a threshold value, and a second proportion when the number of unsatisfied checks is non-zero and is less than the threshold value.

13. The data processing system of claim 12 , wherein the system is implemented as an integrated circuit.

14. The data processing system of claim 12 , wherein the system is implemented as part of a device selected from a group consisting of: a communication device, and a storage device.

15. The data processing system of claim 12 , wherein the system is implemented as an integrated circuit.

16. A data processing system, the data processing system comprising:
a data detector circuit operable to apply a data detection algorithm to a data input to yield a first detector output, and to reapply the data detection algorithm to the data input to yield a second detector output;
a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output;
a data decoder circuit operable to apply a data decoding algorithm to a decoder input derived from the combined detector output to yield a decoded output and a number of unsatisfied checks; and
wherein the comb

Assignees

• Lsi Corp
• Avago Technologies General Ip

Inventors

• Zhang Fan
• Li Shu
• Xiao Jun
• Nguyen Kaitlyn T

Classifications

• H03M13/6331

  Error control coding in combination with equalisation · CPC title

• H04L2201/06

  using the output of a maximum likelihood decoder (Viterbi detector) · CPC title

• H03M13/6583

  Normalization other than scaling, e.g. by subtraction · CPC title

• H03M13/1111 Primary

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title