Phase change memory with switch (PCMS) write error detection

Patent metadata

Field	Value
Publication number	US-9274885-B2
Application number	US-201113997246-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
Phase Change Memory (PCM) controller logic to control access to one or more PCM devices;
a first storage unit to store a single bit to indicate whether an error corresponding to a write operation in any of the one or more PCM devices has occurred; and
one or more storage units to each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCM devices, wherein any one of the one or more PCM devices is capable to assert the single bit, wherein once the single bit is asserted, only the PCM controller logic is capable to de-assert the single bit.

2. The apparatus of claim 1 , wherein the one or more PCM devices are to assert a signal on an error pin to cause the single bit to be updated to indicate the error.

3. The apparatus of claim 1 , wherein each of the one or more PCM devices are to assert a signal on an error pin to cause one of the plurality of bits of the one or more storage units to be updated to indicate the error in the partition.

4. The apparatus of claim 1 , wherein each of the one or more PCM devices are to assert a signal on an error pin to cause at least two of the plurality of bits of the one or more storage units to be updated to indicate the error in the partition and another partition of the one or more PCM devices.

5. The apparatus of claim 1 , wherein the one or more PCM devices are on a same integrated circuit die.

6. The apparatus of claim 1 , wherein the PCM controller logic is to update the single bit to de-assert the error.

7. The apparatus of claim 1 , wherein the one or more PCM devices are to assert a signal on an error pin to indicate the error, wherein the error pin assertion is to occur on a deterministic time interval after a write command is issued to the one or more PCM devices by the PCM controller logic.

8. The apparatus of claim 1 , wherein one or more of the PCM controller logic, a memory, the one or more PCM devices, and a processor core are on a same integrated circuit die.

9. The apparatus of claim 1 , wherein a memory controller is to comprise the PCM controller logic.

10. The apparatus of claim 1 , wherein the first storage unit is to comprise a status register.

11. The apparatus of claim 1 , wherein the one or more storage units are to comprise one or more status registers.

12. A method comprising:
storing a single bit in a first storage unit to indicate whether an error corresponding to a write operation in any of one or more PCM devices has occurred; and
storing a plurality of bits in each of one or more storage units to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCM devices, wherein any one of the one or more PCM devices is capable to assert the single bit, wherein once the single bit is asserted, only a PCM controller logic is capable to de-assert the single bit.

13. The method of claim 12 , further comprising the PCM controller logic controlling access to the one or more PCM devices.

14. The method of claim 12 , further comprising the one or more PCM devices asserting a signal on an error pin to cause the single bit to be updated to indicate the error.

15. The method of claim 12 , further comprising the one or more PCM devices asserting a signal on an error pin to cause one of the plurality of bits of the one or more storage units to be updated to indicate the error in the partition.

16. The method of claim 12 , further comprising the one or more PCM devices asserting a signal on an error pin to cause at least two of the plurality of bits of the one or more storage units to be updated to indicate the error in the partition and another partition of the one or more PCM devices.

17. The method of claim 12 , further comprising updating the single bit to de-assert the error.

18. The method of claim 12 , further comprising the one or more PCM devices asserting a signal on an error pin to indicate the error, wherein the error pin assertion is to occur on a deterministic time interval after a write command is issued to the one or more PCM devices by the PCM controller logic.

19. The method of claim 12 , wherein the first storage unit or the one or more storage units are to comprise one or more status registers.

20. A system comprising:
one or more PCM devices;
a processor to access data stored on the one or more PCM devices via a PCM controller logic;
a first storage unit to store a single bit to indicate whether an error corresponding to a write operation in any of the one or more PCM devices has occurred; and
one or more storage units to each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a first partition of a plurality of partitions of the one or more PCM devices, wherein any one of the one or more PCM devices is capable to assert the single bit, wherein once the single bit is asserted, only the PCM controller logic is capable to de-assert the single bit.

21. The system of claim 20 , wherein the one or more PCM devices are to assert a signal on an error pin to cause the single bit to be updated to indicate the error.

22. The system of claim 20 , wherein each of the one or more PCM devices are to assert a signal on an error pin to cause one of the plurality of bits of the one or more storage units to be updated to indicate the error in the partition.

23. The system of claim 20 , wherein each of the one or more PCM devices are to assert a signal on an error pin to cause at least two of the plurality of bits of the one or more storage units to be updated to indicate the error in the partition and another partition of the one or more PCM devices.

24. The system of claim 20 , wherein the one or more PCM devices are on a same integrated circuit die.

25. The system of claim 20 , wherein the PCM controller logic is to update the single bit to de-assert the error.

26. The apparatus of claim 1 , wherein the one or more storage units are to comprise one or more status registers, wherein each of the one or more status registers is to at least store the single bit and an address of the partition of the plurality of partitions of the one or more PCM devices.

Assignees

• Qawami Shekoufeh
• Sundaram Rajesh
• Intel Corp

Inventors

• Qawami Shekoufeh
• Sundaram Rajesh

Classifications

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/0763

  by bit configuration check, e.g. of formats or tags · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title