Cascaded communication of serialized data streams through devices and their resulting operation

Patent metadata

Field	Value
Publication number	US-9270397-B2
Application number	US-201213658960-A
Country	US
Kind code	B2
Filing date	Oct 24, 2012
Priority date	Oct 24, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

In one embodiment, an apparatus cascades groups of serialized data streams through devices, and performs operations based on information communicated therein. A received group of serialized data streams is aligned, but not framed, and forwarded to a next device (e.g., a next stage in a linear or tree cascaded formation of devices). Eliminating the framing and subsequent serialization operations performed on the received group of serialized data streams reduces the latency of communications through the cascaded devices, which can be significant when considered in relation to the high-speed communication rates. The received group of serialized data streams is also framed to create a sequence of data frames for processing (e.g., associative memory lookup operations, controlling multiplexing of received downstream serialized data streams, general or other processing) within the device.

First claim

What is claimed is:

1. An apparatus, comprising:
a first integrated circuit device, including:
a first interface configured to receive a first plurality of serialized data streams from a source external to the first integrated circuit device;
first framing circuitry, communicatively coupled to the first interface, configured to produce a first sequence of data frames from the first plurality of serialized data streams;
processing circuitry configured to perform operations based on the first sequence of data frames and to generate a second sequence of data frames;
first phase aligning circuitry, communicatively coupled to the first interface, configured to align, but not frame, the first plurality of serialized data streams to produce a first aligned plurality of serialized data streams;
a second interface configured to produce the first aligned plurality of serialized data streams from the first integrated circuit device, with the first aligned plurality of serialized data streams not being framed within the first integrated circuit device;
second framing circuitry configured to produce a second plurality of serialized data streams based on the second sequence of data frames; and
a third interface configured to produce the second plurality of serialized data streams from the first integrated circuit device.

2. The apparatus of claim 1 , wherein said processing circuitry includes associative memory circuitry configured to perform a lookup operation, based on a lookup word generated from, or included in, the first sequence of data frames, to produce a first lookup result;
wherein said processing circuitry is configured to include the first lookup result in the second sequence of data frames.

3. The apparatus of claim 1 , wherein the first integrated circuit device includes:
a fourth interface configured to receive a third plurality of serialized data streams from a source external to the first integrated circuit device; and
third framing circuitry, communicatively coupled to the fourth interface, configured to produce a third sequence of data frames from the third plurality of serialized data streams;
wherein said processing circuitry is configured to perform operations based on the first sequence of data frames and on the third sequence of data frames.

4. The apparatus of claim 3 , wherein said processing circuitry includes associative memory circuitry configured to perform a lookup operation, based on a lookup word generated from, or included in, the first sequence of data frames, to produce a first lookup result;
wherein the third sequence of data frames includes a second lookup result corresponding to an associative memory lookup operation performed in response to an instruction included in the first aligned plurality of serialized data streams; and
wherein said processing circuitry is configured to determine an integrated circuit device lookup result based on the first lookup result and the second lookup result, and to include the integrated lookup result in the second sequence of data frames.

5. The apparatus of claim 4 , including a second integrated circuit device communicatively coupled to receive the first aligned plurality of serialized data streams and to generate the third plurality of serialized data streams;
wherein the second integrated circuit device includes associative memory circuitry configured to perform a lookup operation, based on a lookup word generated from, or included in, the first aligned plurality of serialized data streams, to produce the second lookup result.

6. The apparatus of claim 3 , including a second integrated circuit device communicatively coupled to receive the first aligned plurality of serialized data streams and to generate the third plurality of serialized data streams; and
wherein the second integrated circuit device includes associative memory circuitry configured to perform a lookup operation, based on a lookup word generated from, or included in, the first aligned plurality of serialized data streams, to produce a second lookup result included in the third plurality of serialized data streams;
wherein said processing circuitry includes associative memory circuitry configured to perform a lookup operation, based on a lookup word generated from, or included in, the first sequence of data frames, to produce a first lookup result;
wherein said associative memory circuitry of the first integrated circuit device has a higher priority than said associative memory circuitry of the second integrated circuit device; and
wherein said processing circuitry is configured to determine an integrated circuit device lookup result based on the first lookup result and said higher priority of said associative memory circuitry of the first integrated circuit device prior to receiving the second lookup result, and to include the integrated lookup result in the second sequence of data frames.

7. The apparatus of claim 3 , including a second integrated circuit device communicatively coupled to receive the first aligned plurality of serialized data streams and to generate the third plurality of serialized data streams;
wherein the second integrated circuit device includes general processing circuitry, without associative memory circuitry, configured to perform operations based on one or more instructions generated from, or included in, the first aligned plurality of serialized data streams, and to produce one or more results included in the third plurality of serialized data streams.

8. The apparatus of claim 7 , wherein the first integrated circuit device is configured to include said one or more results in the second sequence of data frames and the second plurality of serialized data streams.

9. The apparatus of claim 3 , wherein said perform operations based on the first sequence of data frames and on the third sequence of data frames includes processing according to one or more instructions in the third sequence of data frames which were received in the third plurality of serialized data streams.

10. The apparatus of claim 3 , wherein the first integrated circuit device includes:
second phase aligning circuitry, communicatively coupled to the first interface, configured to align, but not frame, the first plurality of serialized data streams to produce a second aligned plurality of serialized data streams;
a fifth interface configured to produce the second aligned plurality of serialized data streams from the first integrated circuit device, with the second aligned plurality of serialized data streams not being framed within the first integrated circuit device;
a sixth interface configured to receive a fourth plurality of serialized data streams from a source external to the first integrated circuit device; and
fourth framing circuitry, communicatively coupled to the sixth interface, configured to produce a fourth sequence of data frames from the fourth plurality of serialized data streams; and
wherein said processing circuitry is configured to perform operations based on the first sequence of data frames, based on the third sequence of data frames, and based on the fourth sequence of data frames.

11. An apparatus, comprising:
a first integrated circuit device, including:
a first interface configured to receive a first plurality of serialized data streams from a source external to the first integrated circuit device;
first framing circuitry, communicatively coupled to the first interface, configured to produce a first sequence of data frames from the first plurality of serialized data streams;
processing circuitry configured to perform operations based on the first sequence of data frames;
first phase aligning circuitry, communicatively co

Assignees

• Marshall John W
• Holmes Steven Philip
• Shaw Jeffrey Nelson
• Lipman Michael E
• Harper Matthew
• Tatar Mohammed Ismael
• Markevitch James A
• Cisco Tech Inc

Inventors

• Marshall John W
• Holmes Steven Philip
• Shaw Jeffrey Nelson
• Lipman Michael E
• Harper Matthew
• Tatar Mohammed Ismael
• Markevitch James A

Classifications

• H04J3/0685 Primary

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title

• H04J3/047

  Distributors with transistors or integrated circuits · CPC title