System for reducing noise in a chemical sensor array

Patent metadata

Field	Value
Publication number	US-9270264-B2
Application number	US-201414333754-A
Country	US
Kind code	B2
Filing date	Jul 17, 2014
Priority date	May 29, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

First claim

The invention claimed is:

1. A system comprising:
a power supply;
a clock circuitry to generate a plurality of clock signals, each clock signal of the plurality of clock signals being synchronous with a primary clock signal, and the first, second, and third clock signals of the plurality of clock signals being asynchronous to each other; and
a plurality of switchers, each switcher of the plurality of switchers communicatively coupled to the power supply and the clock circuitry, wherein
a first switcher of the plurality of switchers receives the first clock signal, a second switcher of the plurality of switchers receives the second clock signal, and a third switcher of the plurality of switchers receives the third clock signal,
the first, second and third switchers are disposed on the same substrate,
the first, second, and third clock signals have different frequencies,
the first clock signal has a frequency greater than a frequency of the second clock signal and the second clock signal has a frequency greater than the frequency of the third clock signal, wherein the frequency of the first clock signal is a multiple of the frequency of the second clock signal and is a multiple of the frequency of the third clock signal, and
a rising edge of the first clock signal is offset in a range of ½ to (n−1)/2 cycles of the primary clock signal, where “n” is the number of cycles of the primary clock signal in a cycle of the second clock signal.

2. The system of claim 1 , further comprising a linear regulator coupled to the first switcher.

3. The system of claim 1 , wherein the frequency of the second clock signal is a multiple of the frequency of the third clock signal.

4. The system of claim 1 , wherein a rising edge of the first clock signal is offset by at least ½ cycle of the primary clock signal from the rising edge of the second clock signal.

5. The system of claim 1 , wherein the first and second clock signals have the same frequency.

6. The system of claim 1 , wherein the first and second clock signals have offset rising edges.

7. The system of claim 6 , wherein the offset rising edge is offset by at least ½ cycles of the primary clock signal.

8. The system of claim 7 , wherein the offset is at least two cycles of the primary clock signal.

9. The system of claim 1 , wherein the first clock signal and a fourth clock signal of the plurality of clock signals have the same frequency, the fourth clock signal having a falling edge synchronous with a rising edge of the first clock signal.

10. A method of providing power to a circuitry, the method comprising:
supplying power with a power supply to a plurality of switcher;
generating a plurality of clock signals with a clock circuitry, each of the plurality of clock signals being synchronous with a primary clock signal, and the first, second, and third clock signals of the plurality of clock signals being asynchronous to each other; and
supplying the first clock signal to a first switcher, the second clock signal to a second switcher, and the third clock signal to a third switcher, the first, second and third switchers being of the plurality of switchers, wherein the first, second and third switcher are disposed on the same substrate, the first, second, and third clock signals have different frequencies, the first clock signal has a frequency greater than a frequency of the second clock signal and the second clock signal has a frequency greater than the frequency of the third clock signal, and the frequency of the first clock signal is a multiple of the frequency of the second clock signal and is a multiple of the frequency of the third clock signal, and a rising edge of the first clock signal is offset in a range of ½ to (n−1)/2 cycles of the primary clock signal, where “n” is the number of cycles of the primary clock signal in a cycle of the second clock signal.

11. The method of claim 10 , wherein a fourth clock signal of the plurality of clock signals is provided to the first switcher.

12. The method of claim 10 , wherein the first and second clock signals have offset rising edges.

13. The method of claim 10 , further comprising a linear regulator coupled to the first switcher.

14. The method of claim 1 , wherein the frequency of the second clock signal is a multiple of the frequency of the third clock signal.

Assignees

• Life Technologies Corp

Inventors

• Jordan Jeremy
• Rearick Todd

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03K19/00346

  Modifications for eliminating interference or parasitic voltages or currents · CPC title

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• G01N27/4145 Primary

  specially adapted for biomolecules, e.g. gate electrode with immobilised receptors · CPC title