Amplifier apparatus and methods using variable capacitance dependent on feedback gain

Patent metadata

Field	Value
Publication number	US-9270232-B2
Application number	US-201213618156-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Nov 29, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

An apparatus includes an operational amplifier circuit comprising at least one operational amplifier and a feedback circuit coupled between the output terminal and input terminal of the operational amplifier circuit and configured to apply a feedback gain to an output signal at the output of the first operational amplifier. The apparatus further includes a variable compensation capacitor coupled to the output terminal of the operational amplifier circuit and configured to vary a capacitance thereof responsive to the feedback gain.

First claim

What is claimed is:

1. An apparatus comprising:
an operational amplifier circuit comprising at least one operational amplifier;
a feedback circuit coupled between an output terminal and an input terminal of the operational amplifier circuit and configured to apply a feedback gain to an output signal at the output terminal of the operational amplifier circuit; and
a variable compensation capacitor coupled to the output terminal of the operational amplifier circuit and configured to vary a capacitance thereof responsive to the feedback gain, wherein the capacitance of the variable compensation capacitor decreases to increase stability and decrease bandwidth in an operation period in which the feedback gain is less than 1 and wherein the capacitance of the variable compensation capacitor increases in a reset period in which the feedback gain is 1.

2. The apparatus of claim 1 , wherein the variable compensation capacitor is coupled in parallel with a load capacitance at the output terminal of the operational amplifier circuit.

3. The apparatus of claim 1 , wherein the operational amplifier circuit comprises first and second operational amplifiers coupled in cascade, wherein the feedback circuit is coupled between an output terminal of the second operational amplifier and an input terminal of the first operational amplifier, and wherein the variable compensation capacitor is coupled between the output terminal of the second operational amplifier and an input terminal of the second operational amplifier.

4. The apparatus of claim 1 , further comprising a series combination of a capacitor and a switch coupled in parallel with the variable compensation capacitor.

5. A correlated double sampling (CDS) integrator circuit comprising the apparatus of claim 1 .

6. The integrator circuit of claim 5 , further comprising:
a first capacitor configured to be charged with an input signal and to transfer a charge;
a second capacitor connected between the first capacitor and the input terminal of the operational amplifier circuit;
a third capacitor coupled to the output terminal of the operational amplifier circuit; and
a switching circuit coupled to the first, second and third capacitors and configured to charge the first capacitor and the third capacitor with charges corresponding to image and reset samples and to charge the second capacitor with a charge corresponding to an input offset voltage of the operational amplifier circuit such that a signal at the output terminal of the operational amplifier circuit represents a difference between the image and reset samples.

7. The integrator circuit of claim 6 , wherein the switching circuit comprises a switch configured to short the third capacitor responsive to a reset signal and wherein the variable compensation capacitor increases in capacitance when the reset signal is active.

8. An image sensor circuit comprising:
an analog processor circuit comprising the integrator circuit of claim 5 and configured to sample and amplify an input analog signal; and
an analog-to-digital converter circuit configured to convert an analog signal output from the analog processor circuit into a digital signal.

9. An electronic device comprising the image sensor circuit of claim 8 .

10. An electronic system comprising the image sensor circuit of claim 8 .

11. An apparatus comprising:
a differential amplifier circuit;
a common-gate amplifier circuit coupled to an output terminal of the differential amplifier circuit;
a feedback circuit coupled between an output terminal of the common-gate amplifier circuit and an input terminal of the differential amplifier circuit and configured to apply a feedback gain to an output signal at the output terminal of the common-gate amplifier circuit; and
a variable compensation capacitor coupled to the output terminal of the common gate amplifier circuit and configured to vary a capacitance thereof responsive to the feedback gain, wherein the capacitance of the variable compensation capacitor decreases responsive to the feedback gain decreasing below 1 in an operation period to increase stability and decrease bandwidth and wherein the capacitance of the variable compensation capacitor increases responsive to the feedback gain increasing to 1 in a reset period.

12. The apparatus of claim 11 , wherein the variable compensation capacitor is coupled between the output terminal of the differential amplifier circuit and the output terminal of the common-gate amplifier circuit.

13. The apparatus of claim 11 , wherein the variable compensation capacitor is coupled in parallel with a load capacitance at the output of the common-gate amplifier circuit.

14. The apparatus of claim 11 , further comprising a series combination of another capacitor and a switch coupled in parallel with the variable compensation capacitance.

15. An image sensor comprising an analog signal processor circuit configured to receive signals from a pixel array and comprising the apparatus of claim 11 .

Assignees

• Park Yu Jin
• Kang Soon Hwa
• Kwon Min Ho
• Kim Jae Hong
• Yoo Kwi Sung
• Lim Seung Hyun
• Samsung Electronics Co Ltd

Inventors

• Park Yu Jin
• Kang Soon Hwa
• Kwon Min Ho
• Kim Jae Hong
• Yoo Kwi Sung
• Lim Seung Hyun

Classifications

• H03F1/086

  with FET's · CPC title

• H03F3/45188

  Non-folded cascode stages · CPC title

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title

• H03F2203/45512

  the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC · CPC title

• G11C27/026

  associated with an amplifier (G11C27/028 takes precedence) · CPC title