Integrated circuit power management module

Patent metadata

Field	Value
Publication number	US-9270174-B2
Application number	US-201313892293-A
Country	US
Kind code	B2
Filing date	May 12, 2013
Priority date	May 12, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

An integrated circuit includes a set of electronic circuits, a voltage regulator, and a power management module. The power management module includes a set of dummy circuits connected to the set of electronic circuits, a control signal generator, a counter and a shift register. The control signal generator generates a control signal based on the current consumption of the set of electronic circuits dropping below a threshold value over a predefined period of time. The counter generates a count signal for a predetermined time period when the control signal is activated. The shift register receives the count signal, enables the dummy circuits when the count signal is received, and disables the dummy circuits in a daisy chain fashion during the predetermined time period.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a set of electronic circuits;
a voltage regulator, connected to the set of electronic circuits, for providing a core supply voltage to the set of electronic circuits; and
a power management module, connected to the set of electronic circuits and the voltage regulator, wherein the power management module includes:
a set of dummy circuits connected to the set of electronic circuits;
a control signal generator that generates a control signal based on the current consumption of the set of electronic circuits dropping below a threshold value over a first predetermined time period;
a counter, connected to the control signal generator, that generates a count signal for a second predetermined time period when the control signal is activated; and
a shift register, connected to the counter and the set of dummy circuits, that receives the count signal, enables the set of dummy circuits substantially simultaneously when the count signal is received, and disables the set of dummy circuits in a daisy chain fashion during the second predetermined time period, wherein enabling and then disabling the dummy circuits prevents a sharp change in current consumption, which prevents a high voltage detection signal from being generated and a corresponding reset occurring.

2. The integrated circuit of claim 1 , wherein the second predetermined time period is based on a bandwidth of the voltage regulator and a depth of the set of dummy circuits.

3. The integrated circuit of claim 2 , wherein the depth of the set of dummy circuits is based on a total current consumption of the set of electronic circuits and current consumption of each dummy circuit.

4. The integrated circuit of claim 1 , wherein each dummy circuit of the set of dummy circuits includes an n-type metal oxide semiconductor (NMOS) transistor having a gate terminal connected to an output of the shift register, a source terminal connected to ground, and a drain terminal connected to an output of the voltage regulator.

5. The integrated circuit of claim 1 , wherein the shift register generates a set of dummy control signals to enable and disable the set of dummy circuits.

6. The integrated circuit of claim 1 , wherein the shift register disables the set of dummy circuits in the daisy chain fashion with a gap of a third predetermined time period.

7. The integrated circuit of claim 1 , wherein the control signal generator comprises a high voltage warning (HVW) signal generator that generates the control signal when the core supply voltage increases beyond a predetermined threshold voltage.

8. An integrated circuit, comprising:
a set of electronic circuits;
a voltage regulator, connected to the set of electronic circuits, for providing a core supply voltage to the set of electronic circuits; and
a power management module, connected to the set of electronic circuits and the voltage regulator, wherein the power management module includes:
a set of dummy n-type metal oxide semiconductor (NMOS) transistors, each having a gate terminal, a source terminal connected to ground, and a drain terminal connected to an output of the voltage regulator for receiving the core supply voltage;
a control signal generator that generates a control signal based on a current consumption of the set of electronic circuits dropping below a threshold value over a first predetermined time period;
a counter, connected to the control signal generator, that generates a count signal for a second predetermined time period when the control signal is generated; and
a shift register, connected to the counter and the gate terminals of the set of dummy NMOS transistors, that receives the count signal and generates a set of dummy control signals for enabling the set of dummy NMOS transistors substantially simultaneously when the count signal is received, and disabling the set of dummy NMOS transistors in a daisy chain fashion during the second predetermined time period.

9. The integrated circuit of claim 8 , wherein the second predetermined time period is based on a bandwidth of the voltage regulator and a depth of the set of the dummy NMOS transistors.

10. The integrated circuit of claim 9 , wherein the depth of the set of dummy NMOS transistors is based on a total current consumption of the set of electronic circuits and the current consumption of each dummy NMOS transistor.

11. The integrated circuit of claim 8 , wherein the shift register disables the set of dummy NMOS transistors in the daisy chain fashion with a gap of a third predetermined time period.

12. The integrated circuit of claim 8 , wherein the control signal generator includes a high voltage warning (HVW) signal generator that generates the control signal when the core supply voltage increases beyond a predetermined threshold voltage.

Assignees

• Miyan Lalit Mohan Singh
• Abhishek Kumar
• Singh Nitin
• Freescale Semiconductor Inc

Inventors

• Miyan Lalit Mohan Singh
• Abhishek Kumar
• Singh Nitin

Classifications

• H02M2003/1566

  Electricity · mapped topic

• H02M3/157 Primary

  with digital control · CPC title

• Y10T307/406

  Cross-Sectional Technologies · mapped topic

• H02M3/1566

  with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title