DC-DC converter and semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9270157-B2
Application number	US-201313913023-A
Country	US
Kind code	B2
Filing date	Jun 7, 2013
Priority date	Jul 25, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A DC-DC converter includes: a high-side switch; a low-side switch coupled to the high-side switch in series; a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage; a buffer configured to output a control signal for controlling the high-side switch; a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and a switch configured to receive the control signal from the latch and deactivate the buffer.

First claim

What is claimed is:

1. A DC-DC converter comprising:
a high-side switch;
a low-side switch coupled to the high-side switch in series;
a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage;
a buffer configured to output a control signal for controlling the high-side switch;
a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and
a switch, including a transistor provided between the buffer and a low-voltage power line and including a control terminal for receiving the control signal from the latch and configured to deactivate the buffer based on the control signal.

2. The DC-DC converter according to claim 1 , further comprising:
a second buffer configured to receive an inverted signal of the control signal and output the inverted signal to a second input terminal of the latch.

3. The DC-DC converter according to claim 2 , wherein the latch continues to output, in accordance with the inverted signal, the control signal for turning on the high-side switch to the high-side switch after deactivation of the buffer.

4. The DC-DC converter according to claim 2 , further comprising:
a second switch configured to deactivate the second buffer in accordance with the control signal for turning off the high-side switch from the latch.

5. The DC-DC converter according to claim 1 , wherein the high-side switch has a N-type polarity.

6. The DC-DC converter according to claim 1 , further comprising:
a diode disposed between the high-side switch and the capacitor.

7. The DC-DC converter according to claim 1 , wherein the switch is further configured to deactivate the buffer by interrupting a path between the buffer and the low-voltage power line based on the control signal.

8. The DC-DC converter according to claim 1 , further comprising:
an auxiliary buffer provided between the latch and the high-side switch, the auxiliary buffer being configured to supply a signal obtained by inverting the control signal to the latch.

9. A semiconductor integrated circuit comprising:
a DC-DC converter including:
a high-side switch;
a low-side switch coupled to the high-side switch in series;
a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage;
a buffer configured to output a control signal for controlling the high-side switch;
a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch;
a switch configured to receive the control signal from the latch and deactivate the buffer based on the control signal; and
an auxiliary buffer, provided between the latch and the high-side switch and configured to supply a signal obtained by inverting the control signal to the latch; and

an inductor coupled to a connection node between the high-side switch and the low-side switch.

10. The semiconductor integrated circuit according to claim 9 , wherein the DC-DC converter and the inductor are arranged on a single chip.

11. The semiconductor integrated circuit according to claim 9 , wherein the DC-DC converter further comprises:
a second buffer configured to receive an inverted signal of the control signal and output the inverted signal to a second input terminal of the latch.

12. The semiconductor integrated circuit according to claim 11 , wherein the latch continues to output, in accordance with the inverted signal, the control signal for turning on the high-side switch to the high-side switch after deactivation of the buffer.

13. The semiconductor integrated circuit according to claim 11 , wherein the DC-DC converter includes a second switch configured to deactivate the second buffer in accordance with the control signal for turning off the high-side switch from the latch.

14. The semiconductor integrated circuit according to claim 9 , wherein the high-side switch has a N-type polarity.

15. The semiconductor integrated circuit according to claim 9 , wherein the DC-DC converter includes a diode disposed between the high-side switch and the capacitor.

16. The semiconductor integrated circuit according to claim 9 , wherein the switch is further configured to include a transistor provided between the buffer and a low-voltage power line and including a control terminal for receiving the control signal from the latch.

17. The semiconductor integrated circuit according to claim 9 , wherein the switch is further configured to deactivate the buffer by interrupting a path between the buffer and a low-voltage power line based on the control signal.

18. A DC-DC converter comprising:
a high-side switch;
a low-side switch coupled to the high-side switch in series;
a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage;
a buffer coupled to a low-voltage power line and configured to output a control signal for controlling the high-side switch;
a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and
a switch configured to receive the control signal from the latch and deactivate the buffer by interrupting a path between the buffer and the low-voltage power line based on the control signal.

19. The DC-DC converter according to claim 18 , wherein the switch is further configured to include a transistor provided between the buffer and the low-voltage power line and to include a control terminal for receiving the control signal from the latch.

20. The DC-DC converter according to claim 18 , further comprising:
an auxiliary buffer provided between the latch and the high-side switch, the auxiliary buffer being configured to supply a signal obtained by inverting the control signal to the latch.

Assignees

• Fujitsu Ltd

Inventors

• Kondou Masafumi
• Mori Toshihiko

Classifications

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H02M2001/0006

  Electricity · mapped topic

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/1588

  comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title