Self-aligned interconnection for integrated circuits

Patent metadata

Field	Value
Publication number	US-9269747-B2
Application number	US-201213593065-A
Country	US
Kind code	B2
Filing date	Aug 23, 2012
Priority date	Aug 23, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

First claim

What is claimed is:

1. A memory device, comprising one or more storage cells individually comprising a selector transistor having a buried silicon component in substantially direct contact with an electrically conductive vertical contact electrically coupled to a horizontal electrode line, the electrode line having a line width defined by a double-patterning technique, the vertical contact having at least one lateral dimension greater than the line width and confined on at least one edge by a hard mask material.

2. The memory device of claim 1 , wherein the horizontal electrode line comprises a word-line electrode.

3. The memory device of claim 2 , wherein the selector transistor of each of the one or more storage cells comprises a bipolar junction transistor and the buried silicon component comprises a base component of the bipolar junction transistor.

4. The memory device of claim 3 , wherein each of the one or more storage cells comprises a phase change memory material electrically coupled between an emitter of the bipolar transistor and a bit-line electrode.

5. The memory device of claim 4 , wherein the hard mask material comprises a conformal etch stop layer over the bit-line electrode.

6. The memory device of claim 1 , wherein the hard mask material comprises a planar hard mask between an upper insulating layer and a lower insulating layer, wherein the upper insulating layer comprises the horizontal electrode line embedded therein, and the lower insulating layer comprises the vertical contact embedded therein.

7. An integrated circuit comprising:
a first insulating layer;
a second insulating layer over the first insulating layer;
a hard mask formed between the first insulating layer and the second insulating layer, the hard mask including an elongate slot;
a plurality of conductive lines embedded within the second insulating layer, the conductive lines intersecting with the elongate slot of the hard mask at intersections; and
a plurality of conductive contacts extending from the conductive lines at the intersections, through the elongate slot of the hard mask and through the first insulating layer.

Assignees

• Pellizzer Fabio
• Rigano Antonino
• Somaschini Roberto
• Micron Technology Inc

Inventors

• Pellizzer Fabio
• Rigano Antonino
• Somaschini Roberto

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title