ESD protection using diode-isolated gate-grounded nMOS with diode string

Patent metadata

Field	Value
Publication number	US-9269703-B2
Application number	US-201414453907-A
Country	US
Kind code	B2
Filing date	Aug 7, 2014
Priority date	Nov 3, 2010
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising:
forming a gate-grounded NMOS ESD device;
forming an isolation diode in series with and coupled to a source of the gate-grounded NMOS transistor, wherein the isolation diode is segmented and placed in close proximity to, and on opposite sides of, a body of the gate-grounded NMOS ESD device; and
forming a diode string coupled to the gate-grounded NMOS ESD device in a forward biased configuration, wherein diodes of the diode string are segmented and placed on multiple sides of the body of the gate-grounded NMOS ESD device.

2. The method of claim 1 where said diode string is formed with at least 2 diodes in series.

3. The method of claim 2 where said diode string is formed with 3 diodes in series.

4. The method of claim 1 further comprising coupling said diode string between a drain and a source of said gate-grounded NMOS ESD device.

5. The method of claim 1 further comprising coupling said diode string between a source of said gate-grounded NMOS ESD device and a p+ diffusion of the isolation diode in said gate-grounded NMOS ESD device.

6. The method of claim 1 where a p+ substrate contact diffusion surrounds said gate-grounded NMOS ESD device and said diode string.

7. The method of claim 1 further comprising coupling a gate of said gate-grounded NMOS ESD device to ground through a resistor.

Assignees

• Texas Instruments Inc

Inventors

• Pok Ponnarith
• Schulmeyer Kyle
• Cline Roger A
• Duvvury Charvaka

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D89/814

  involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title