Semiconductor device and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9269654-B2
Application number	US-201414180146-A
Country	US
Kind code	B2
Filing date	Feb 13, 2014
Priority date	Jan 18, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip comprising a first coil disposed over a first semiconductor substrate;
an isolating film disposed on the first semiconductor chip;
a second semiconductor chip comprising a second coil and a second semiconductor substrate, wherein the second semiconductor substrate is disposed over the second coil, wherein the second semiconductor chip is attached to the first semiconductor chip with the isolating film, wherein the first coil of the first semiconductor chip is inductively coupled through the isolating film with the second coil of the second semiconductor chip to form a coreless transformer;
a through hole disposed in the second semiconductor substrate, wherein the through hole extends through the entire second semiconductor substrate so as to expose a contact pad, wherein the contact pad is disposed over the contact pad, wherein the contact pad and the second coil are disposed between the second semiconductor substrate and the isolating film; and
an encapsulating material disposed within the through hole in the second semiconductor substrate.

2. The semiconductor package according to claim 1 , wherein the dielectric strength of the isolating film is at least 60 kV/mm.

3. The semiconductor package according to claim 1 , wherein the dielectric strength of the isolating film is less than 100 kV/mm.

4. The semiconductor package according to claim 1 , wherein the isolating film comprises a double side adhesive or a attach paste.

5. The semiconductor package according to claim 1 , wherein the isolating film comprises a thickness of 20 μm to 500 μm.

6. The semiconductor package according to claim 1 , wherein the first semiconductor chip comprises an integrated circuit and wherein the second semiconductor chip consists essentially of the contact pad, the second coil and an electrical connection between the contact pad and the second coil.

7. The semiconductor package according to claim 1 , further comprising a lead frame, wherein a first pad of the first semiconductor chip is wire bonded to the lead frame, and wherein the contact pad of the second semiconductor chip is wire bonded to the lead frame.

8. A semiconductor package comprising:
a lead frame;
a first semiconductor chip comprising a first coil disposed over a first semiconductor substrate, the first semiconductor chip disposed on the lead frame;
a second semiconductor chip comprising a second coil, a second semiconductor substrate and a contact pad, the second semiconductor substrate is disposed over the second coil and the contact pad the second coil aligned with the first coil, the second semiconductor chip disposed on the first semiconductor chip;
an isolating film disposed between the first semiconductor chip and the second semiconductor chip, wherein the second semiconductor chip is attached to the first semiconductor chip with the isolating film, wherein the first coil of the first semiconductor chip is inductively coupled through the isolating film with the second coil of the second semiconductor chip to form a coreless transformer;
a through hole disposed in the second semiconductor substrate, wherein the through hole extends through the entire second semiconductor substrate so as to expose the contact pad, wherein the contact pad and the second coil are disposed between the second semiconductor substrate and the isolating film; and
an encapsulation material encapsulating the first semiconductor chip, the second semiconductor chip, the through hole, and the lead frame.

9. The semiconductor package according to claim 8 , wherein the dielectric strength of the isolating film is at least 60 kV/mm.

10. The semiconductor package according to claim 8 , wherein the dielectric strength of the isolating film is less than 100 kV/mm.

11. The semiconductor package according to claim 8 , wherein the first semiconductor chip comprises an integrated circuit and wherein the second semiconductor chip consists essentially of the contact pad, the second coil and an electrical connection between the pad and the second coil.

12. The semiconductor package according to claim 8 , wherein the first semiconductor chip and the second semiconductor chip are arranged in a face-to-face configuration.

13. The semiconductor package according to claim 8 , wherein the second semiconductor substrate comprises a thickness of less than 300 μm.

14. The semiconductor package according to claim 8 , further comprising a first wire connection between the lead frame and the contact pad of the second semiconductor chip and a second wire connection between the lead frame and a pad of the first semiconductor chip.

15. The semiconductor package according to claim 14 , wherein there is no wire connection between the first semiconductor chip and the second semiconductor chip.

16. The semiconductor package according to claim 14 , wherein the pad of the first semiconductor chip is disposed on a top surface of the first semiconductor chip.

17. The semiconductor package according to claim 8 , wherein the first semiconductor substrate of the first semiconductor chip is connected via a metal bond to the lead frame.

18. The semiconductor package according to claim 8 , wherein the first semiconductor substrate of the first semiconductor chip is connected via an adhesive bond to the lead frame.

19. A semiconductor package comprising:
a first semiconductor chip with a first coil disposed over a first semiconductor substrate;
a second semiconductor chip with a second semiconductor substrate, a second coil and a contact pad, the second semiconductor substrate disposed over the second coil and the contact pad; and
an isolating film disposed between the first semiconductor chip and the second semiconductor chip, wherein the second semiconductor chip is attached to the first semiconductor chip with the isolating film, wherein the first coil of the first semiconductor chip is inductively coupled through the isolating film with the second coil of the second semiconductor chip;
a through hole disposed in the second semiconductor substrate, wherein the through hole extends through the entire second semiconductor substrate so as to expose the contact pad;
a wire disposed within the through hole disposed in the second semiconductor substrate; and
a wire bond disposed in the through hole coupling the wire to the contact pad of the second semiconductor chip.

20. The semiconductor package according to claim 19 , wherein the wire couples the second coil to a lead of a lead frame.

21. The semiconductor package according to claim 19 , further comprising an encapsulation material encapsulating the first semiconductor chip, the second semiconductor chip, the isolating film, the wire, and the wire bond.

22. The semiconductor package according to claim 19 , further comprising an encapsulation material disposed within the through hole in the second semiconductor substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Willkofer Stefan
• Wahl Uwe
• Knott Bernhard
• Hammer Markus
• Strasser Andreas

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title