Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same

Patent metadata

Field	Value
Publication number	US-9269646-B2
Application number	US-201213613235-A
Country	US
Kind code	B2
Filing date	Sep 13, 2012
Priority date	Nov 14, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which may comprise a relatively higher power density region, extends peripherally beyond the stack. Conductive elements extend between and electrically interconnect integrated circuits of semiconductor dice in the stack and of the other semiconductor die. Thermal pillars are interposed between semiconductor dice of the stack, and a heat dissipation structure, such as a lid, is in contact with an uppermost die of the stack and the higher power density region of the other semiconductor die. Other die assemblies, semiconductor devices and methods of managing heat transfer within a semiconductor die assembly are also disclosed.

First claim

What is claimed is:

1. A semiconductor die assembly, comprising:
a plurality of semiconductor dice in a stack;
conductive elements between and interconnecting integrated circuits of the plurality of semiconductor dice in the stack;
thermally conductive structures between the plurality of semiconductor dice in the stack and electrically isolated from the integrated circuits;
a dielectric material located between the plurality of semiconductor dice in the stack and around the conductive elements and the thermally conductive structures;
another semiconductor die located under the plurality of semiconductor dice in the stack, the another semiconductor die comprising a relatively higher power density region within a peripheral area of the another semiconductor die extending laterally beyond the stack; and
a heat dissipation structure disposed over the plurality of semiconductor dice in the stack and the another semiconductor die, the heat dissipation structure in thermal contact with an uppermost die in the stack and with the relatively higher power density region of the another semiconductor die.

2. The semiconductor die assembly of claim 1 , further comprising conductive elements between the another semiconductor die and a lowermost semiconductor die in the stack and dielectric material located between the another semiconductor die and the lowermost semiconductor die in the stack and around the conductive elements.

3. The semiconductor die assembly of claim 2 , wherein there are no electrically isolated thermally conductive structures between the another semiconductor die and the lowermost semiconductor die in the stack.

4. The semiconductor die assembly of claim 1 , wherein the heat dissipation structure is in thermal contact with the uppermost die in the stack and with the relatively higher power density region of the another semiconductor die through a thermal interface material, and is in thermal contact with the substrate through a seal material.

5. The semiconductor die assembly of claim 2 , wherein electrically isolated thermally conductive structures between the another semiconductor die and the lowermost semiconductor die in the stack provide a lesser heat transfer capability than a heat transfer capability provided by the thermally conductive structures between the plurality of semiconductor dice in the stack.

6. The semiconductor die assembly of claim 1 , wherein the electrically isolated thermally conductive structures comprise at least one of thermal pillars or wall structures.

7. The semiconductor die assembly of claim 6 , wherein the electrically isolated thermally conductive structures comprise thermal pillars and the thermal pillars are substantially homogeneously distributed across major surfaces of the plurality of semiconductor dice of the stack.

8. The semiconductor die assembly of claim 6 , wherein the electrically isolated thermally conductive structures comprise thermal pillars and the thermal pillars are non-homogeneously distributed across major surfaces of the plurality of semiconductor dice of the stack.

9. The semiconductor die assembly of claim 6 , wherein the electrically isolated thermally conductive structures comprise thermal pillars, and thermal pillars between two adjacent semiconductor dice in the stack are vertically aligned with thermal pillars between at least one of the two adjacent semiconductor dice in the stack and at least one other semiconductor die in the stack.

10. The semiconductor die assembly of claim 6 , wherein the electrically isolated thermally conductive structures comprise thermal pillars, and at least one thermal pillar between two adjacent semiconductor dice in the stack is laterally offset from at least one other thermal pillar between at least one of the two adjacent semiconductor dice in the stack and at least one other semiconductor die in the stack.

11. The semiconductor die assembly of claim 1 , wherein the electrically isolated thermally conductive structures are interspersed with the conductive elements between the plurality of semiconductor dice of the stack.

12. The semiconductor die assembly of claim 1 , wherein the plurality of semiconductor dice in the stack comprise memory dice, and the another semiconductor die comprises a logic die.

13. A semiconductor device, comprising:
a plurality of memory dice in a stack;
a plurality of thermally conductive structures, other than conductive elements electrically connecting integrated circuits of adjacent memory dice in the stack, between the adjacent memory dice in the stack;
a dielectric material between the adjacent memory dice and around the plurality of thermally conductive structures;
a logic die at a base of the stack and comprising a relatively higher power density region and a relatively lower power density region, wherein at least a portion of the relatively higher power density region extends peripherally beyond at least one side of the stack;
a substrate of greater peripheral lateral extent than the logic die, under the logic die; and
a lid disposed over the stack of memory dice and the logic die in thermal contact with the substrate and in thermal contact with an uppermost memory die of the stack and with the relatively higher power density region of the logic die.

14. The semiconductor device of claim 13 , wherein the plurality of thermally conductive structures comprises at least one of pillars or walls.

15. The semiconductor device of claim 14 , wherein the plurality of thermally conductive structures comprises pillars and the pillars are substantially homogeneously distributed across major surfaces of the plurality of memory dice in the stack.

16. The semiconductor device of claim 14 , wherein the plurality of thermally conductive structures comprises pillars and the pillars are non-homogeneously distributed across major surfaces of the plurality of memory dice in the stack.

17. The semiconductor device of claim 14 , wherein the plurality of thermally conductive structures comprises pillars, and pillars between two adjacent memory dice in the stack are vertically aligned with pillars between at least one of the two adjacent memory dice in the stack and the logic die in the stack.

18. The semiconductor device of claim 14 , wherein the plurality of thermally conductive structures comprises pillars, and at least one pillar between two adjacent memory dice in the stack is laterally offset from at least one other pillar between at least one of the two adjacent memory dice in the stack and the logic die in the stack.

19. The semiconductor device of claim 13 , wherein the plurality of thermally conductive structures is interspersed with conductive elements between the plurality of memory dice of the stack.

20. The semiconductor device of claim 13 , wherein a pattern of the plurality of thermally conductive structures between at least two adjacent memory dice at least partially differs from a pattern of the plurality of thermally conductive structures between at least one of the at least two adjacent memory dice and another memory die.

21. The semiconductor device of claim 13 , wherein the plurality of thermally conductive structures between at least two adjacent memory dice are at least one of sized or arranged to provide a greater heat transfer capability in at least one region within a periphery of the stack than a heat transfer capability in at least one other region within a periphery of the stack.

22. The semiconductor device of claim 13 , further compri

Assignees

• Luo Shijian
• Li Xiao
• Li Jian
• Micron Technology Inc

Inventors

• Luo Shijian
• Li Xiao
• Li Jian

Classifications

• H10W90/724 Primary

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title