Method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9269592-B2
Application number	US-201414464849-A
Country	US
Kind code	B2
Filing date	Aug 21, 2014
Priority date	Dec 31, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a first direction, forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, and doping the source region and the drain region with dopants of a second conductivity type. Forming the drain extension region includes forming a core portion doped with the first conductivity type in the second ridge portion, and forming the drain extension region further includes forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a transistor in a semiconductor substrate, the semiconductor substrate having a first main surface, wherein forming the transistor comprises:
forming a ridge including a first ridge portion and a second ridge portion in the semiconductor substrate, the ridge extending along a first direction,
forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, doping the source region and the drain region with dopants of a second conductivity type,
wherein forming the drain extension region comprises forming a core portion doped with the first conductivity type in the second ridge portion, forming the drain extension region further comprises forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion.

2. The method according to claim 1 , wherein forming the cover portion is performed after forming the gate electrode.

3. The method according to claim 2 , wherein the cover portion is formed in a self-aligned manner with respect to the gate electrode.

4. The method according to claim 2 , wherein forming the cover portion comprises a doping process using the gate electrode as a mask.

5. The method according to claim 1 , further comprising forming a field plate adjacent to the cover portion.

6. The method according to claim 2 , wherein forming the ridge is accomplished so that the second ridge portion has a width different from a width of the first ridge portion.

7. The method according to claim 2 , further comprising forming a gate insulating layer, wherein forming the cover portion comprises performing a selective epitaxy method after forming the gate insulating layer.

Assignees

• Infineon Technologies Ag

Inventors

• Meiser Andreas
• Hirler Franz
• Kampen Christian

Classifications

• H10P32/17

  characterised by the semiconductor material · CPC title

• H10P32/12 Primary

  between a solid phase and a gaseous phase · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D64/111

  Field plates · CPC title