Semiconductor device with increased channel mobility and dry chemistry processes for fabrication thereof

Patent metadata

Field	Value
Publication number	US-9269580-B2
Application number	US-201113229276-A
Country	US
Kind code	B2
Filing date	Sep 9, 2011
Priority date	Jun 27, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a Silicon Carbide substrate comprising a channel region; and
a gate stack on the Silicon Carbide substrate on the channel region, the gate stack comprising:
a first alkaline earth metal layer, an amorphous wide bandgap dielectric layer on the first alkaline earth metal layer, and a second alkaline earth metal layer on the amorphous wide bandgap dielectric layer;
a contact layer on the second alkaline earth metal layer.

2. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is at least 2.5 times greater than that of the same semiconductor device without the alkaline earth metal.

3. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is at least 50 cm 2 V -1 s -1 for control voltages greater than 3 Volts.

4. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is at least 50 cm 2 V -1 s -1 for control voltages in a range of and including 3 Volts to 15 Volts.

5. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is at least 40 cm 2 V -1 s -1 for control voltages greater than 2.5 Volts.

6. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is at least 40 cm 2 V -1 s -1 for control voltages in a range of and including 2.5 Volts to 15 Volts.

7. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is at least 60 cm 2 V -1 s -1 for control voltages greater than 4 Volts.

8. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is at least 60 cm 2 V -1 s -1 for control voltages in a range of and including 4 Volts to 15 Volts.

9. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is in a range of and including 40-75 cm 2 V -1 s -1 for control voltages greater than 2.5 Volts.

10. The semiconductor device of claim 1 wherein a channel mobility of the semiconductor device is in a range of and including 50-75 cm 2 V -1 S -1 for control voltages in a range of and including 3 Volts to 15 Volts.

11. The semiconductor device of claim 1 wherein the first alkaline earth metal layer contains Barium (Ba).

12. The semiconductor device of claim 1 wherein the first alkaline earth metal layer contains Strontium (Sr).

13. The semiconductor device of claim 1 wherein the first alkaline earth metal layer is an oxide containing the alkaline earth metal.

14. The semiconductor device of claim 13 wherein the oxide containing the alkaline earth metal is Barium Oxide.

15. The semiconductor device of claim 13 wherein the oxide containing the alkaline earth metal is Ba X Si Y O Z .

16. The semiconductor device of claim 1 wherein the first alkaline earth metal layer is an oxynitride containing the alkaline earth metal.

17. The semiconductor device of claim 16 wherein the oxynitride is BaO X N Y .

18. The semiconductor device of claim 1 wherein the amorphous wide bandgap dielectric layer comprises an oxide layer formed of one of a group consisting of: Silicon Dioxide (SiO 2 ), Aluminum Oxide (Al 2 O 3 ), and Hafnium Oxide (HfO).

19. The semiconductor device of claim 1 wherein at least one of the first alkaline earth metal layer and the second alkaline earth metal layer contains Barium (Ba).

20. The semiconductor device of claim 1 wherein at least one of the first alkaline earth metal layer and the second alkaline earth metal layer contains Strontium (Sr).

21. The semiconductor device of claim 1 wherein the first alkaline earth metal layer is directly on the surface of the silicon carbide substrate over the channel region.

22. The semiconductor device of claim 1 wherein the gate stack further comprises a gate metal layer on a surface of the second alkaline earth metal layer opposite the oxide layer.

23. The semiconductor device of claim 1 wherein the silicon carbide substrate is one of a group consisting of: a 4H silicon carbide (SiC) substrate, a 6H SiC substrate, a 3C SiC substrate, and a 15R SiC substrate.

24. The semiconductor device of claim 1 wherein the semiconductor device is a lateral Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) further comprising:
a source region formed in the silicon carbide substrate; and
a drain region formed in the silicon carbide substrate;
wherein the gate stack is formed on the silicon carbide substrate between the source and drain regions.

25. The semiconductor device of claim 24 wherein the silicon carbide substrate is one of a group consisting of: a 4H silicon carbide (SiC) substrate, a 6H SiC substrate, a 3C SiC substrate, and a 15R SiC substrate.

26. The semiconductor device of claim 1 wherein the semiconductor device is a vertical Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) further comprising:
a well of a first conductivity type formed in the silicon carbide substrate, the Silicon Carbide substrate being of a second conductivity type;
a source region of the second conductivity type formed in the well, wherein the gate stack is on the silicon carbide substrate and extends over at least a portion of the well and the source region; and
a drain contact on a surface of the silicon carbide substrate opposite the gate stack.

27. The semiconductor device of claim 26 wherein the silicon carbide substrate is one of a group consisting of: a 4H silicon carbide (SiC) substrate, a 6H SiC substrate, a 3C SiC substrate, and a 15R SiC substrate.

28. The semiconductor device of claim 1 wherein the semiconductor device is an Insulated Gate Bipolar Transistor (IGBT) further comprising:
an emitter region formed in the silicon carbide substrate, wherein the gate stack is on the silicon carbide substrate and extends over at least a portion of the emitter region; and
a collector contact on a surface of the silicon carbide substrate opposite the gate stack.

29. The semiconductor device of claim 28 wherein the silicon carbide substrate is one of a group consisting of: a 4H silicon carbide (SiC) substrate, a 6H SiC substrate, a 3C SiC substrate, and a 15R SiC substrate.

30. The semiconductor device of claim 1 wherein the semiconductor device is a trench field effect transistor, and:
the silicon carbide substrate comprises:
a first layer of a first conductivity type;
a drift layer of the first conductivity type on a first surface of the first layer of the

first conductivity type;
a well of a second conductivity type on a surface of the drift layer opposite the

first layer;
a source region of the first conductivity type in or on the well;
a source contact on a surface of the source region opposite the well;
a drain contact on a second surface of the first layer opposite the drift layer; and
a trench that extends from the surface of the source region through the well to the

surface of the drift layer, wherein the gate stack is formed in the trench.

31. The semiconductor device of claim 30 wherein the silicon carbide substrate is one of a group consisting of: a 4H silicon carbide (SiC) substrate, a 6H SiC substrate, a 3C SiC substrate, and a 15R SiC substrate.

32. The semiconductor device of claim 1 wherein the thickness of the amorphous wide ban

Assignees

• Dhar Sarit
• Cheng Lin
• Ryu Sei-Hyung
• Agarwal Anant
• Palmour John Williams
• Gurganus Jason
• Cree Inc

Inventors

• Dhar Sarit
• Cheng Lin
• Ryu Sei-Hyung
• Agarwal Anant
• Palmour John Williams
• Gurganus Jason

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6928

  the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10P14/6938

  the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title