Generating read thresholds using gradient descent and without side information

Patent metadata

Field	Value
Publication number	US-9269449-B2
Application number	US-201414550764-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Jul 6, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A first bit position of a cell in solid state storage is read where a sorting bit is obtained using the read of the first bit position. A second bit position of the cell is read for a first time, including by setting a first read threshold associated with the second bit position to a first value and setting a second read threshold associated with the second bit position to a second value. The second bit position of the cell is read for a second time, including by setting the first read threshold to a third value and setting the second read threshold to a fourth value. A new value for the first read threshold and for the second read threshold is generated using the sorting bit, the first read, and the second read.

First claim

What is claimed is:

1. A system, comprising:
a solid state storage interface configured to:
read a first bit position of a cell in solid state storage, wherein a sorting bit is obtained using the read of the first bit position;
read a second bit position of the cell for a first time, including by:
setting a first read threshold associated with the second bit position to a first read threshold value; and
setting a second read threshold associated with the second bit position to a second read threshold value; and

read the second bit position of the cell for a second time, including by:
setting the first read threshold to a third read threshold value; and
setting the second read threshold to a fourth read threshold value; and

a read threshold generator configured to generate a new value for the first read threshold and a new value for the second read threshold using: (1) the sorting bit, (2) the first read of the second bit position, and (3) the second read of the second bit position.

2. The system of claim 1 , further comprising the solid state storage.

3. The system of claim 2 , wherein the solid state storage includes one or more of following: multi-level cell (MLC) storage and tri-level cell (TLC) storage.

4. The system of claim 1 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

5. The system of claim 1 , wherein the first bit position is a least significant bit (LSB) and the second bit position is a most significant bit (MSB).

6. The system of claim 1 , wherein:
the read of the first bit position returns an uncorrected bit; and
the system further includes an error correction decoder configured to error correction decode the uncorrected bit in order to obtain a corrected bit, wherein the corrected bit is used as the sorting bit.

7. The system of claim 1 , wherein the read threshold generator is configured to generate a new value for the first read threshold and a new value for the second read threshold, including by:
incrementing a first count, associated with a number of cells between the first read threshold value and the third read threshold value, in the event: (1) the value of the sorting bit is a first bit value and (2) the second bit position of the cell changes values between the first read of the second bit position and the second read of the second bit position, wherein the first count is used to generate a new value for the first read threshold; and
incrementing a second count, associated with a number of cells between the second read threshold value and the fourth read threshold value, in the event: (1) the value of the sorting bit is a second bit value and (2) the second bit position of the cell changes values between the first read of the second bit position and the second read of the second bit position, wherein the second count is used to generate a new value for the second read threshold.

8. The system of claim 1 , wherein the read threshold generator is configured to generate a new value for the first read threshold and a new value for the second read threshold, including by:
incrementing a first count, associated with the first read threshold, in the event: (1) the value of the sorting bit is a first bit value and (2) the first read of the second bit position returns a specified value, wherein the first count is used to generate a new value for the first read threshold;
incrementing a second count, associated with the second read threshold, in the event: (1) the value of the sorting bit is a second bit value and (2) the first read of the second bit position returns a specified value, wherein the second count is used to generate a new value for the second read threshold;
incrementing a third count, associated with the first read threshold, in the event: (1) the value of the sorting bit is a first bit value and (2) the second read of the second bit position returns a specified value, wherein the third count is used to generate a new value for the first read threshold; and
incrementing a fourth count, associated with the second read threshold, in the event: (1) the value of the sorting bit is a second bit value and (2) the second read of the second bit position returns a specified value, wherein the fourth count is used to generate a new value for the second read threshold.

9. A method, comprising:
reading a first bit position of a cell in solid state storage, wherein a sorting bit is obtained using the read of the first bit position;
reading a second bit position of the cell for a first time, including by:
setting a first read threshold associated with the second bit position to a first read threshold value; and
setting a second read threshold associated with the second bit position to a second read threshold value;

reading the second bit position of the cell for a second time, including by:
setting the first read threshold to a third read threshold value; and
setting the second read threshold to a fourth read threshold value; and

using a processor to generate a new value for the first read threshold and a new value for the second read threshold using: (1) the sorting bit, (2) the first read of the second bit position, and (3) the second read of the second bit position.

10. The method of claim 9 , wherein the solid state storage includes one or more of following: multi-level cell (MLC) storage and tri-level cell (TLC) storage.

11. The method of claim 9 , wherein the processor includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

12. The method of claim 9 , wherein the first bit position is a least significant bit (LSB) and the second bit position is a most significant bit (MSB).

13. The method of claim 9 , wherein:
the read of the first bit position returns an uncorrected bit; and
the method further includes performing error correction decoding on the uncorrected bit in order to obtain a corrected bit, wherein the corrected bit is used as the sorting bit.

14. The method of claim 9 , wherein generating a new value for the first read threshold and a new value for the second read threshold includes:
incrementing a first count, associated with a number of cells between the first read threshold value and the third read threshold value, in the event: (1) the value of the sorting bit is a first bit value and (2) the second bit position of the cell changes values between the first read of the second bit position and the second read of the second bit position, wherein the first count is used to generate a new value for the first read threshold; and
incrementing a second count, associated with a number of cells between the second read threshold value and the fourth read threshold value, in the event: (1) the value of the sorting bit is a second bit value and (2) the second bit position of the cell changes values between the first read of the second bit position and the second read of the second bit position, wherein the second count is used to generate a new value for the second read threshold.

15. The method of claim 9 , wherein generating a new value for the first read threshold and a new value for the second read threshold includes:
incrementing a first count, associated with the first read threshold, in the event: (1) the value of the sorting bit is a first bit value and (2) the first read of the second bit position returns a specified value, wherein the first count is used to generate a new value for the first read thre

Assignees

• Sk Hynix Memory Solutions Inc

Inventors

• Lee Frederick K H
• Bellorado Jason
• Subramanian Arunkumar
• Zeng Lingqi
• Tang Xiangyu
• Aslam Ameen

Classifications

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title