Information processing device including host device and semiconductor memory device having plurality of address conversion information

Patent metadata

Field	Value
Publication number	US-9268706-B2
Application number	US-201213561392-A
Country	US
Kind code	B2
Filing date	Jul 30, 2012
Priority date	Aug 1, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

First claim

What is claimed is:

1. An information processing device comprising a host device and a semiconductor memory device,
the host device comprising a main memory, and
the semiconductor memory device comprising
a nonvolatile semiconductor memory which stores first address conversion information and data,
a memory unit which stores second address conversion information, the second address conversion information being part of the first address conversion information, and
a controller which accesses the nonvolatile semiconductor memory by referring to the second address conversion information,
wherein third address conversion information is stored in the main memory, the third address conversion information being part of or all of the first address conversion information, and the controller uses the third address conversion information when accessing the nonvolatile semiconductor memory if address conversion information to be referred is not stored in the second address conversion information.

2. The device according to claim 1 , wherein
the controller, when using the third address conversion information, refers to the address conversion information to be referred stored in the third address conversion information after transferred to the second address conversion information.

3. The device according to claim 1 , wherein
the nonvolatile semiconductor memory further comprises a Dynamic Memory Access (DMA) controller, and
the DMA controller transfers address conversion information from the third address conversion information to the second address conversion information.

4. The device according to claim 1 , wherein
the host device secures an area of the main memory, read part of or all of the first address conversion information stored in the nonvolatile semiconductor memory, and stores the read part of or all of the first address conversion information as the third address conversion information in the secured area of the main memory.

5. The device according to claim 1 , wherein
the controller, when the address conversion information to be referred is not stored in the second address conversion information, executes an interrupt to the host device and acquires the address conversion information to be referred from the third address conversion information.

6. The device according to claim 1 , wherein
the host device, when the address conversion information to be referred is not stored in the main memory, acquires the address conversion information to be referred from the first address conversion information.

7. A semiconductor memory device comprising:
a nonvolatile semiconductor memory which stores first address conversion information and data,
a memory unit which stores second address conversion information, the second address conversion information being part of the first address conversion information, and
a controller which accesses the nonvolatile semiconductor memory by referring to the second address conversion information,
wherein the controller refers to second address conversion information to be referred acquired from an external of the semiconductor memory device and accesses the nonvolatile semiconductor memory when accessing the nonvolatile semiconductor memory if address conversion information to be referred is not stored in the second address conversion information.

8. The device according to claim 7 , further comprising a Dynamic Memory Access (DMA) controller,
wherein the DMA controller acquires the address conversion information to be referred from the external of the semiconductor memory device.

Assignees

• Kunimatsu Atsushi
• Maeda Kenichi
• Toshiba Kk

Inventors

• Kunimatsu Atsushi
• Maeda Kenichi

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F11/1458

  Management of the backup or restore process · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title