Snoop filter having centralized translation circuitry and shadow tag array

Patent metadata

Field	Value
Publication number	US-9268697-B2
Application number	US-201213730956-A
Country	US
Kind code	B2
Filing date	Dec 29, 2012
Priority date	Dec 29, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing cores; and
snoop filter logic circuitry coupled to said plurality of processing cores, said snoop filter logic circuitry having translation circuitry and a tag array, said translation circuitry to identify a physical address for a cache line in response to receipt at said snoop filter logic circuitry of a snoop request with a virtual address of said cache line from any one of said processing cores, said tag array to identify from the physical address from the translation circuitry which of said plurality of processing cores is caching said cache line and where said cache line is cached in a respective cache of said one which of said plurality of processing cores is caching said cache line.

2. The processor of claim 1 wherein said snoop filter logic circuitry is to insert into said tag array an identifier of said cache line's location in said respective cache as part of processing said snoop request.

3. The processor of claim 2 wherein said snoop filter logic circuitry does not implement said insert if a core that sends said snoop request is the same as the core that is determined to be holding said cache line.

4. The processor of claim 1 wherein said snoop filter logic circuitry is to send a forwarded version of said snoop request to said which of said plurality of processing cores is caching said cache line, said forwarded version containing information identifying where said cache line is cached in said respective cache.

5. The processor of claim 4 wherein said which of said plurality of processing cores is caching said cache line contains logic circuitry to use said information to fetch said cache line.

6. The processor of claim 1 further comprising an interconnection network between said plurality of processing cores and said snoop filter logic circuitry.

7. The processor of claim 1 wherein said snoop filter logic circuitry is within coherence plane logic circuitry of a last level cache of said processor.

8. A method comprising:
performing a virtual address based cache look-up for a cache line in a first processing core;
determining at said first processing core that the virtual address based cache look-up is a miss;
sending a snoop request with a virtual address of said cache line from said first processing core to a snoop filter;
performing a virtual address to physical address translation within said snoop filter to determine a physical address for said virtual address;
using said physical address within said snoop filter to determine which processing core of a plurality of processing cores is caching said cache line and determine location information to indicate where said cache line is being cached within a cache that is caching said cache line;
sending said location information to whichever processing core was determined to be caching said cache line; and
said processing core determined to be caching said cache line using said location information to fetch said cache line.

9. The method of claim 8 wherein said processing core determined to be caching said cache line is different than said processing core and sends said cache line to said processing core.

10. The method of claim 9 wherein said snoop filter sends said location information along with an identity of said processing core to said processing core determined to be caching said processing core.

11. The method of claim 9 wherein said processing core sends second location information as part of said snoop request, said second location information identifying where said cache line will be cached within a cache of said processing core upon its receipt of said cache line.

12. The method of claim 11 further comprising said snoop filter updating an array by replacing said location information with said second location information.

13. The method of claim 8 wherein said processing core determined to be caching said cache line is said processing core.

14. The method of claim 9 wherein said processing core sends second location information as part of said snoop request, said second location information identifying where said cache line will be cached within a cache of said processing core upon its receipt of said cache line, and said snoop filter does not replace said location information with said second location information.

15. A processor comprising:
a plurality of processing cores each having a first level cache; and
snoop filter logic circuitry in a second level cache and coupled to said first level caches of the plurality of processing cores, said snoop filter logic circuitry having translation circuitry and a tag array, said translation circuitry to identify a physical address for a cache line in response to receipt at said snoop filter logic circuitry of a snoop request with a virtual address of said cache line from any one of said processing cores, said tag array to identify from the physical address from the translation circuitry which of said plurality of processing cores is caching said cache line and where said cache line is cached in a respective first level cache of said which of said plurality of processing cores is caching said cache line.

16. The processor of claim 15 wherein said snoop filter logic circuitry is to insert into said tag array an identifier of said cache line's location in said respective cache as part of processing said snoop request.

17. The processor of claim 16 wherein said snoop filter logic circuitry does not implement said insert if a core that sends said snoop request is the same as the core that is determined to be holding said cache line.

18. The processor of claim 15 wherein said snoop filter logic circuitry is to send a forwarded version of said snoop request to said which of said plurality of processing cores is caching said cache line, said forwarded version containing information identifying where said cache line is cached in said respective cache.

19. The processor of claim 18 wherein said which of said plurality of processing cores is caching said cache line contains logic circuitry to use said information to fetch said cache line.

20. The processor of claim 15 wherein said second level cache is a last level cache.

Assignees

• Pardo Ilan
• Cooray Niranjan
• Shwartsman Stanislav
• Raikin Shlomo
• Intel Corp

Inventors

• Pardo Ilan
• Cooray Niranjan
• Shwartsman Stanislav
• Raikin Shlomo

Classifications

• G06F12/0822 Primary

  Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831) · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1063

  the data cache being concurrently virtually addressed · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title