Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
US9268685B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9268685-B2 |
| Application number | US-201313953065-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 29, 2013 |
| Priority date | Mar 22, 2013 |
| Publication date | Feb 23, 2016 |
| Grant date | Feb 23, 2016 |
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According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value.
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What is claimed is: 1. A memory system comprising: a non-volatile semiconductor memory including a plurality of memory chips which can be operated in parallel and each of memory chips is divided into a plurality of planes capable of operating in parallel, each of the planes including a plurality of physical blocks as a unit of data erasing; and a controller configured to control the non-volatile semiconductor memory, wherein the controller includes: a virtual block management…
Physics · mapped topic
Physics · mapped topic
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