System on a chip serial communication interface method and apparatus

Patent metadata

Field	Value
Publication number	US-9268661-B1
Application number	US-201414293475-A
Country	US
Kind code	B1
Filing date	Jun 2, 2014
Priority date	Sep 14, 2006
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A method performable by a communication interface configured to interface between a first device and a second device, the method comprising:
receiving a first serial signal stream from the first device;
converting, within a predetermined time, the first serial signal stream to a first parallel signal stream, wherein the first parallel signal stream comprises a plurality of signal streams that are to be transmitted in parallel;
transmitting the first parallel signal stream to the second device;
receiving a second signal stream from the first device;
transmitting the second signal stream to the second device; and
subsequent to receiving the second signal stream from the first device, delaying the transmission of the second signal stream to the second device by an amount of time that accounts for the predetermined time taken to convert the first serial signal stream to the first parallel signal stream, wherein the amount of time by which the transmission of the second signal stream to the second device is delayed is substantially equal to the predetermined time taken to convert the first serial signal stream to the first parallel signal stream.

2. The method of claim 1 , wherein the first device is a system on a chip (SoC).

3. The method of claim 2 , wherein the second device is a test unit configured to test the SoC.

4. A method performable by a communication interface configured to interface between a first device and a second device, the method comprising:
receiving a first serial signal stream from the first device;
converting, within a predetermined time, the first serial signal stream to a first parallel signal stream, wherein the first parallel signal stream comprises a plurality of signal streams that are to be transmitted in parallel;
transmitting the first parallel signal stream to the second device;
receiving a second signal stream from the first device;
transmitting the second signal stream to the second device; and
subsequent to receiving the second signal stream from the first device, delaying the transmission of the second signal stream to the second device by an amount of time that accounts for the predetermined time taken to convert the first serial signal stream to the first parallel signal stream,
wherein the communication interface is a first communication interface,
wherein the first device is a system on a chip (SoC) comprising (i) a second communication interface and (ii) a read channel block, and
wherein the first serial signal stream is received by the first communication interface from the read channel block of the SoC, via the second communication interface of the SoC.

5. The method of claim 4 , wherein the second device is a test unit configured to test the read channel block of the SoC.

6. The method of claim 4 , wherein:
the second signal stream is received by the first communication interface from the read channel block of the SoC, by bypassing the second communication interface of the SoC.

7. The method of claim 1 , further comprising:
receiving a third parallel signal stream from the second device, wherein the third parallel signal stream comprises another plurality of signal streams that are received in parallel;
converting the third parallel signal stream to a third serial signal stream; and
transmitting the third serial signal stream to the first device.

8. A communication interface configured to interface between a first device and a second device, the communication interface comprising:
logic configured to
receive a first serial signal stream from the first device,
convert, within a predetermined time, the first serial signal stream to a first parallel signal stream, wherein the first parallel signal stream comprises a plurality of signal streams that are to be transmitted in parallel, and
transmit the first parallel signal stream to the second device; and

a delay module configured to
receive a second signal stream from the first device,
transmit the second signal stream to the second device, and
subsequent to receiving the second signal stream from the first device, delay the transmission of the second signal stream to the second device by an amount of time that accounts for the predetermined time taken by the logic to convert the first serial signal stream to the first parallel signal stream, wherein the amount of time by which the transmission of the second signal stream to the second device is delayed is substantially equal to the predetermined time taken to convert the first serial signal stream to the first parallel signal stream.

9. The communication interface of claim 8 , wherein the first device is a system on a chip (SoC).

10. The communication interface of claim 9 , wherein the second device is a test unit configured to test the SoC.

11. A communication interface configured to interface between a first device and a second device, the communication interface comprising:
logic configured to
receive a first serial signal stream from the first device,
convert, within a predetermined time, the first serial signal stream to a first parallel signal stream, wherein the first parallel signal stream comprises a plurality of signal streams that are to be transmitted in parallel, and
transmit the first parallel signal stream to the second device; and

a delay module configured to
receive a second signal stream from the first device,
transmit the second signal stream to the second device, and
subsequent to receiving the second signal stream from the first device, delay the transmission of the second signal stream to the second device by an amount of time that accounts for the predetermined time taken by the logic to convert the first serial signal stream to the first parallel signal stream,

wherein the communication interface is a first communication interface
wherein the first device is a system on a chip (SoC) comprising (i) a second communication interface and (ii) a read channel block, and
wherein the first serial signal stream is received by the logic of the first communication interface from the read channel block of the SoC, via the second communication interface of the SoC.

12. The communication interface of claim 11 , wherein the second device is a test unit configured to test the read channel block of the SoC.

13. The communication interface of claim 11 , wherein:
the second signal stream is received by the logic of the first communication interface from the read channel block of the SoC, by bypassing the second communication interface of the SoC.

14. The communication interface of claim 8 , wherein the logic is first logic and the communication interface further comprises:
second logic configured to
receive a third parallel signal stream from the second device, wherein the third parallel signal stream comprises another plurality of signal streams that are received in parallel,
convert the third parallel signal stream to a third serial signal stream, and
transmit the third serial signal stream to the first device.

Assignees

• Marvell Int Ltd

Inventors

• Longstreet Roger
• Khanzode Vivek Raghunath
• Sheng Hongying

Classifications

• G06F11/273 Primary

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• G06F13/1684

  using multiple buses · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title