Error correction using multiple data sources

Patent metadata

Field	Value
Publication number	US-9268635-B2
Application number	US-201414284103-A
Country	US
Kind code	B2
Filing date	May 21, 2014
Priority date	May 21, 2014
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A data storage device includes a memory and a controller. A method includes accessing data stored at the memory to generate a first logical page. The method further includes generating a second logical page. Generating the second logical page includes accessing parity information from the memory. The parity information is associated with the first logical page. The method further includes generating a third logical page. Generating the third logical page includes modifying a first value of the first logical page based on a second bit value of the second logical page.

First claim

What is claimed is:

1. A method comprising:
in a data storage device that includes a controller and a memory coupled to the controller, performing by the controller:
accessing data stored at the memory to generate a first logical page;
generating a second logical page, wherein generating the second logical page includes accessing parity information from the memory, the parity information associated with the first logical page; and
generating a third logical page, wherein generating the third logical page includes modifying a first value of the first logical page based on a second value of the second logical page.

2. The method of claim 1 , wherein the first value is modified based on reliability information associated with the first logical page.

3. The method of claim 1 , wherein the first value is modified based on reliability information associated with the second logical page.

4. The method of claim 1 , wherein the third logical page is a binary page of hard bits, and wherein modifying the first value includes replacing the first value with the second value.

5. The method of claim 4 , wherein the first value is replaced with the second value in response to reliability information associated with the first logical page indicating that the first value has low reliability.

6. The method of claim 4 , wherein the first value is replaced with the second value in response to reliability information associated with the second logical page indicating that the first value has low reliability.

7. The method of claim 1 , wherein the third logical page includes log-likelihood ratio (LLR) values, and wherein modifying the first value includes summing a first LLR value corresponding to the first value with a second LLR value corresponding to the second value.

8. The method of claim 1 , wherein the second logical page is a reconstructed version of the first logical page that is generated using the parity information.

9. The method of claim 8 , wherein the second logical page is generated by performing an exclusive-or (XOR) operation with respect to the parity information and at least one other logical page stored at the memory.

10. The method of claim 8 , wherein the second logical page is generated in response to a first decoding failure associated with the first page.

11. The method of claim 10 , wherein the third logical page is generated in response to a second decoding failure associated with the second page, and further comprising decoding the third logical page to generate user data.

12. The method of claim 1 , wherein the third logical page is generated without attempting to decode one or both of the first logical page or the second logical page.

13. The method of claim 1 , further comprising, prior to accessing the parity information, generating the parity information by performing an exclusive-or (XOR) operation with respect to the first logical page and at least one other logical page stored at the memory.

14. The method of claim 13 , wherein the first logical page and the at least one other logical page each include data bits and error correcting code (ECC) bits.

15. The method of claim 1 , wherein the first value is modified in response to reliability information indicating that the second value is more reliable than the first value.

16. The method of claim 15 , further comprising generating a reference page including a first set of first logical values indicating that corresponding values of the first logical page are unreliable and further including a second set of second logical values indicating that corresponding values of the first logical page are reliable, wherein the reliability information corresponds to the reference page.

17. The method of claim 15 , further comprising generating the reliability information using a soft read technique that senses a physical page to generate the first logical page.

18. The method of claim 15 , further comprising generating the reliability information using a neighbor read technique that senses a physical page of the memory, wherein the physical page is adjacent to a target physical page of the memory, the target physical page storing the data.

19. The method of claim 15 , further comprising generating the reliability information using a bad column indicator that indicates unreliability of a column of the memory.

20. The method of claim 15 , further comprising generating the reliability information using a shaping technique that assigns a first probability to a first logical value and a second probability to a second logical value.

21. The method of claim 1 , wherein the memory is a non-volatile memory having a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device includes circuitry associated with operation of the memory cells.

22. A data storage device comprising:
a memory; and
a controller, wherein the controller is coupled to the memory, wherein the controller is configured to access a first logical page stored at the memory and to generate a second logical page, wherein generating the second logical page includes accessing parity information from the memory, the parity information associated with the first logical page, and wherein the controller is further configured to generate a third logical page, wherein generating the third logical page includes modifying a first value of the first logical page based on a second value of the second logical page.

23. The data storage device of claim 22 , further comprising a decoder, wherein the decoder is configured to decode the third logical page in response to a decoding failure of at least one of the first logical page or the second logical page.

24. The data storage device of claim 23 , wherein the first value and the second value are soft values, and wherein the decoder is a soft-input decoder.

25. The data storage device of claim 23 , wherein the first value and the second value are hard bits, and wherein the decoder is a hard-input decoder.

26. The data storage device of claim 25 , wherein the decoder is a Bose-Chaudhuri-Hocquenghem (BCH) decoder.

27. The data storage device of claim 22 , wherein the controller includes a page combiner, and wherein the page combiner is configured to generate the third logical page.

28. The data storage device of claim 22 , wherein the memory includes read/write circuitry, wherein the first value is modified in response to reliability information indicating that the second value has a higher reliability than the first value, and wherein the read/write circuitry is configured to generate the reliability information using a soft read technique.

29. The data storage device of claim 28 , wherein the reliability information includes log-likelihood ratio (LLR) values associated with the first logical page or the second logical page.

30. The data storage device of claim 22 , wherein the memory is a non-volatile memory having a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device includes circuitry associated with operation of the memory cells.

Assignees

• Sandisk Technologies Inc

Inventors

• Sharon Eran
• Navon Ariel
• Presman Noam

Classifications

• H03M13/2927

  Decoding strategies · CPC title

• H03M13/45

  Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence) · CPC title

• H03M13/2957

  Turbo codes and decoding · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• H03M13/2909

  Product codes · CPC title