Application scheduling in heterogeneous multiprocessor computing platform based on a ratio of predicted performance of processor cores

Patent metadata

Field	Value
Publication number	US-9268611-B2
Application number	US-89065310-A
Country	US
Kind code	B2
Filing date	Sep 25, 2010
Priority date	Sep 25, 2010
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.

First claim

The invention claimed is:

1. A processor with application scheduling using performance-based core modeling prediction heuristics comprising:
a storage unit to store a performance history table (PHT), said PHT including performance statistics, and one or more performance counters, said performance counters corresponding to performance of an application having been executed on one or more of a plurality of heterogeneous processor cores of the processor; and
logic to determine whether a first processor core of the plurality of processor cores is to execute the application based, at least in part, on a ratio of predicted performance of the application if it were executed on the first processor core versus on another processor core of the plurality of processor cores, the performance to be predicted for the first processor core from the one or more performance counters of said another processor core, and to cause scheduling of the application for execution on the first processor core whenever said ratio of predicted performance on the first processor core versus said another processor core indicates either one of the larger performance gains or one the smaller performance losses, wherein said ratio of predicted performance is predicted from an issue width ratio on the first processor core versus said another processor core as diminished by one or more predicted stall factor ratios, and
wherein the logic is to transmit data to an operating system to cause scheduling of the application on the first processor core.

2. The processor of claim 1 , wherein the logic is to transmit data to the operating system to cause scheduling of the application on the first processor core in response to detection of a context switch.

3. The processor of claim 1 , wherein the stored PHT corresponding to the performance of the application having been executed on one or more of the plurality of processor cores of the processor is to comprise execution performance data or power consumption performance data.

4. The processor of claim 1 , wherein the logic is to update the stored PHT based on collected information.

5. The processor of claim 1 , wherein the logic is to predict execution performance or power consumption performance of the application on at least some of the plurality of processor cores.

6. The processor of claim 1 , wherein the application is scheduled for execution on the first processor core whenever said ratio of predicted performance on the first processor core versus said another processor core indicates either one of the larger performance gains or one the smaller performance losses in comparison to all applications available to be scheduled.

7. The processor of claim 1 , wherein the storage unit is to comprise: a shared memory, a private cache, a shared cache, or a dedicated memory.

8. The processor of claim 1 , wherein the stored PHT is stored in a process control block of the application.

9. The processor of claim 1 , wherein the storage unit is to store a performance history table (PHT) including performance statistics for each application executing on one or more of the plurality of processor cores.

10. The processor of claim 9 , wherein each entry in the PHT is to at least store a process identifier and a plurality cycles per instruction corresponding to the plurality of processor cores.

11. The processor of claim 1 , wherein the storage unit is to store one or more performance counters for each application executing on one or more of the plurality of processor cores.

12. The processor of claim 11 , wherein the one or more performance counters are to comprise: core clock cycles, instructions retired, level 2 cache misses, scheduler stalls, resource stalls, or branch stalls.

13. A method comprising:
storing a performance history table (PHT), said PHT including performance statistics, and one or more performance counters, said performance counters corresponding to performance of an application having been executed on one or more of a plurality of heterogeneous processor cores of a processor;
determining whether a first processor core of the plurality of processor cores is to execute an application based, at least in part, on a ratio of predicted performance of the application if it were executed on the first processor core versus on another processor core of the plurality of processor cores, the performance to be predicted for the first processor core from the one or more performance counters of said another processor core; and
scheduling the application for execution on the first processor core in response to a transmission of data corresponding to the first processor core to an operating system whenever said ratio of predicted performance on the first processor core versus said another processor core indicates either one of the larger performance gains or one the smaller performance losses, wherein said ratio of predicted performance is predicted from an issue width ratio on the first processor core versus said another processor core as diminished by one or more predicted stall factor ratios.

14. The method of claim 13 , wherein the transmission of data is to be in response to detection of a context switch.

15. The method of claim 13 , wherein the stored PHT corresponding to the performance of the application having been executed on one or more of the plurality of processor cores of the processor is to comprise execution performance data or power consumption performance data.

16. The method of claim 13 , further comprising updating the stored PHT based on collected information.

17. The method of claim 13 , further comprising predicting execution performance or power consumption performance of the application on at least some of the plurality of processor cores.

18. The method of claim 13 , wherein storing the PHT is in a process control block of the application.

19. The method of claim 13 , wherein
each entry in the PHT is to at least store a process identifier and a plurality cycles per instruction corresponding to the plurality of processor cores; or one or more performance counters, wherein the one or more performance counters are to comprise: core clock cycles, instructions retired, level 2 cache misses, scheduler stalls, resource stalls, or branch stalls.

20. A computing system comprising:
a processor comprising a plurality of heterogeneous processor cores; and
a storage unit to store a performance history table (PHT), said PHT including performance statistics, and one or more performance counters, said performance counters corresponding to performance of an application having been executed on one or more of the plurality of processor cores of the processor, wherein at least one of the plurality of processor cores is to comprise logic to determine whether a first processor core of the plurality of processor cores is to execute an application based, at least in part, on a ratio of predicted performance of the application if it were executed on the first processor core versus on another processor core of the plurality of processor cores, the performance to be predicted for the first processor core from the one or more performance counters of said another processor core, and to cause scheduling of the application for execution on the first processor core whenever said ratio of predicted performance on the first processor core versus said another processor core indicates either one of the larger performance gains or one the smaller performance losses, wherein said ratio of predicted performance is predicted from an issue width ra

Assignees

• Iyer Ravishankar
• Srinivasan Sadagopan
• Zhao Li
• Illikkal Rameshkumar G
• Intel Corp

Inventors

• Iyer Ravishankar
• Srinivasan Sadagopan
• Zhao Li
• Illikkal Rameshkumar G

Classifications

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• G06F12/084

  with a shared cache · CPC title

• G06F11/3409

  for performance assessment · CPC title

• Y02B60/165

  Cross-Sectional Technologies · mapped topic