Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

Patent metadata

Field	Value
Publication number	US-9268598-B2
Application number	US-201213615416-A
Country	US
Kind code	B2
Filing date	Sep 13, 2012
Priority date	Sep 13, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

First claim

What is claimed is:

1. A processor core comprising:
a transactional memory that stores information corresponding to a plurality of atomic memory transactions executed by the processor core, wherein the transactional memory includes transactional memory logic that, for each of a plurality of aborted transactions among the plurality of atomic memory transactions, generates a respective one of a plurality of indications that an abort-causing conflict has occurred during execution of one of the plurality of aborted transactions;
an instruction address register for recording instruction addresses of abort-causing and approximate abort-causing instructions, wherein the instruction address register, responsive to each of the plurality of indications generated by the transactional memory logic, records a respective instruction address for each of the plurality of aborted transactions, wherein for at least some of the plurality of aborted transactions, the instruction address recorded in the instruction address register is that of an abort-causing instruction and, for at least some of the plurality of aborted transactions, the instruction address recorded in the instruction address register is that of an approximate abort-causing instruction in the aborted transaction different than and following the abort-causing instruction;
a transaction diagnostic register that, responsive to each of the plurality of indications generated by the transactional memory logic, records a first validity indication associated with a respective one of the plurality of aborted transactions, wherein the processor core indicates, via a first state of the first validity indication, that the instruction address recorded in the instruction address register is that of an abort-causing instruction, and indicates, via a second state of the first validity indication, that the instruction address recorded in the instruction address register is that of an approximate abort-causing instruction;
a data address register for recording data addresses of abort-causing and approximate abort-causing instructions;
a second validity indication associated with the second address register that indicates, via first and second states of the second validity indication, whether a data address recorded in the data address register is that of an abort-causing instruction or an approximate abort-causing instruction in the aborted transaction, respectively;
wherein the processor core is configured to:
retrieve the addresses corresponding to each of the plurality of aborted transactions from the instruction and data address registers; and
generate profiling information of the plurality of aborted transactions based on the retrieved addresses and the validity indications.

2. The processor core of claim 1 , wherein the processor core is further configured to store addresses of abort-causing instructions in a first profiling data structure and to store addresses of approximate abort-causing instructions in a separate second profiling data structure.

3. The processor core of claim 1 , wherein the processor core is further configured to periodically retrieve the addresses from the instruction and data address registers for profiling based on a user-specified frequency.

4. The processor core of claim 1 , wherein the profiling information includes:
identifying information regarding a function in which the abort-causing conflict occurred; and
an event count indicating a number of conflicts detected in the function.

5. The processor core of claim 1 , wherein the transactional memory comprises a lower level cache memory.

6. A computer program product for use with a computer for recording and profiling information of a plurality of aborted transactions among a plurality of atomic memory transactions executed by a processing core, wherein the processing core includes an instruction address register, a data address register, a transaction diagnostic register, and a transactional memory, wherein the transactional memory includes transactional memory logic that, for each of a plurality of aborted transactions among the plurality of atomic memory transactions, generates a respective one of a plurality of indications that an abort-causing conflict has occurred during execution of one of the plurality of aborted transactions, the computer program product comprising:
a non-transitory computer-readable storage device; and
program code, stored within the computer-readable storage device, that when executed causes the processor core to perform:
in response to each of the plurality of indications generated by the transactional memory logic, recording, in the instruction address register, a respective instruction address for each of the plurality of aborted transactions, wherein for at least some of the plurality of aborted transactions, the instruction address recorded in the instruction address register is that of an abort-causing instruction and, for at least some of the plurality of aborted transactions, the instruction address recorded in the instruction address register is that of an approximate abort-causing instruction in the aborted transaction different than and following the abort-causing instruction;
in response to each of the plurality of indications generated by the transactional memory logic, recording, in the transaction diagnostic register, a first validity indication associated with a respective one of the plurality of aborted transactions, wherein the transaction diagnostic register indicates, via a first state of the first validity indication, that the instruction address recorded in the instruction address register is that of an abort-causing instruction in the aborted transaction, and indicates, via a second state of the first validity indication, that the instruction address recorded in the instruction address register is that of an approximate abort-causing instruction;
in response to each of the plurality of indications generated by the transactional memory logic, recording, in the data address register, a respective data address for each of the plurality of aborted transactions, wherein for at least some of the plurality of aborted transactions, the data address recorded in the data address register is that of an abort-causing instruction and, for at least some of the plurality of aborted transactions, the data address recorded in the data address register is that of an approximate abort-causing instruction;
in response to each of the plurality of indications generated by the transactional memory logic, recording, in the transaction diagnostic register, a second validity indication associated with the second address register that indicates, via first and second states of the second validity indication, whether a data address recorded in the second address register is that of an abort-causing instruction or an approximate abort-causing instruction in the aborted transaction, respectively;
retrieving the addresses corresponding to each of the plurality of aborted transactions from the instruction and data address registers; and
generating profiling information of the plurality of aborted transactions based on the retrieved addresses and the validity indications.

7. The computer program product claim 6 , wherein the program code, when executed, causes the processor core to perform:
storing the addresses of abort-causing instructions in a first profiling data structure and storing the addresses of approximate abort-causing instructions in a separate second profiling data structure.

8. The computer program product claim 6 , wherein the program code, when executed, causes the processor core to perform:
periodically retrieving addresses from the instruction and data address registers for profiling based on a user-sp

Assignees

• Blainey Robert J
• Cain Harold W
• Eisen Susan E
• Frey Bradly G
• Hall Charles B
• Le Hung Q
• May Cathy
• IBM

Inventors

• Blainey Robert J
• Cain Harold W
• Eisen Susan E
• Frey Bradly G
• Hall Charles B
• Le Hung Q
• May Cathy

Classifications

• G06F11/3648

  using additional hardware · CPC title

• G06F11/1474 Primary

  in transactions (updating of structured data in databases G06F16/23) · CPC title

• G06F11/36

  Prevention of errors by analysis, debugging or testing of software · CPC title

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title