Method and apparatus to use DRAM as a cache for slow byte-addressible memory for efficient cloud applications
US-12174739-B2 · Dec 24, 2024 · US
Information processor
US9268486B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9268486-B2 |
| Application number | US-201514799795-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 15, 2015 |
| Priority date | Jun 8, 2012 |
| Publication date | Feb 23, 2016 |
| Grant date | Feb 23, 2016 |
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Abstract
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An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.
First claim
Opening claim text (preview).
What is claimed is: 1. An information processor comprising: an information processing sub-system; and a plurality of memory sub-systems performing data communication with the information processing sub-system, wherein: the information processing sub-system has an information processing circuit for processing a graph according to graph processing instructions, the memory sub-system has a first memory, a second memory having reading and writing latencies longer than those of…
Assignees
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Physics · mapped topic
Physics · mapped topic
- G06F12/08Primary
Physics · mapped topic
- G06F3/0611Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9268486B2 cover?
- An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a me…
- Who is the assignee on this patent?
- Hitachi Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F12/08. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 23 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).