Implementing dynamic regulator output current limiting

Patent metadata

Field	Value
Publication number	US-9268347-B2
Application number	US-201313764858-A
Country	US
Kind code	B2
Filing date	Feb 12, 2013
Priority date	Feb 12, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A method and apparatus are provided for implementing dynamic regulator output current limiting. An input power to the regulator is measured, and the measured input power is related to a regulator output current and a regulator over current trip point, and dynamically used for providing dynamic regulator output current limiting.

First claim

What is claimed is:

1. An apparatus for implementing dynamic regulator output current limiting comprising:
a regulator includes a regulator input receiving an input voltage and input power and said regulator including a redundant regulator system;
a controller coupled to said regulator; said controller receiving a measured input power of said regulator input and said controller receiving an operational mode from said regulator of operational modes of N+2, N+1, phase or phases running;
said controller relating the measured input power to a regulator output current and a regulator over current trip point, and said controller dynamically providing regulator output current limiting; said controller decreasing a load frequency only in operational node N when the measured input power is greater than a regulator over current threshold and enabling running at full frequency in operational modes N+2, N+1.

2. The apparatus as recited in claim 1 includes an inline shunt resistor in said regulator input being used to measure the regulator input power.

3. The apparatus as recited in claim 2 includes a hardware operational amplifier (Op-amp) comparator circuit connected to said inline shunt resistor.

4. The apparatus as recited in claim 3 includes a high speed comparator; the measured input power being read with said high speed comparator.

5. The apparatus as recited in claim 1 includes said controller receiving vital product data (VPD) from said regulator.

6. The apparatus as recited in claim 1 further includes said controller changing a soft over current (OC) trip point as a function of said operational modes of N+2, N+1 or N phase or phases running.

7. The apparatus as recited in claim 1 wherein said controller relating the measured input power to a regulator output current includes said controller identifying a multiplier as a function of the current regulator output voltage set point, and said controller using said identified multiplier Bf(Pvid) to identify a current capping limit CCAP.

8. A method for implementing dynamic regulator output current limiting comprising:
providing a regulator includes a regulator input receiving an input voltage and input power and providing a redundant regulator system;
providing a controller coupled to said regulator;
said controller receiving a measured input power of said regulator input and said controller receiving an operational mode from said regulator of operational modes of N+2,N+1, or N phases running;
said controller relating the measured input power to a regulator output current and a regulator over current trip point,
said controller dynamically providing regulator output current limiting; and
said controller decreasing a load frequency only in operational mode N when the measured input power is greater than a regulator over current threshold and enabling running at full frequency in operational modes N+2, N+1.

9. The method as recited in claim 8 includes providing an inline shunt resistor in said regulator input; and using said inline shunt resistor to measure the regulator input power.

10. The method as recited in claim 9 wherein using said inline shunt resistor to measure the regulator input power includes providing a hardware operational amplifier (Op-amp) comparator circuit connected to said inline shunt resistor.

11. The method as recited in claim 9 includes providing a high speed comparator; and reading the measured input power with said high speed comparator DAC.

12. The method as recited in claim 8 includes said controller receiving vital product data (VPD) from said regulator.

13. The method as recited in claim 8 includes said controller changing a soft over current (OC) trip point as a function of said operational modes of N+2, N+1 or N phase or phases running.

14. The method as recited in claim 8 includes said controller identifying a multiplier as a function of the current regulator output voltage set point, and said controller using said identified multiplier to identify a current capping limit CCAP.

15. The method as recited in claim 8 includes said controller comparing a measured input current to said regulator with an identified current capping limit.

16. The method as recited in claim 15 includes said controller decreasing a regulator output load responsive to said measured input current being greater than said identified current capping limit.

17. The method as recited in claim 15 includes said controller increasing a regulator output load responsive to said measured input current being less than said identified current capping limit.

18. The method as recited in claim 15 includes said controller identifying a multiplier as a function of the current regulator output voltage set point responsive to said compared measured input current and said identified current capping limit.

19. The method as recited in claim 8 wherein said controller relating the measured input power to said regulator output current and said regulator over current trip point includes said controller measuring an average input current during a set time interval.

Assignees

• IBM

Inventors

• Covi Kevin R
• Egan Patrick K
• Jordan James D
• Keuseman Jordan R
• Miller Michael L
• Silva Guillermo J
• Allen-Ware Malcolm S

Classifications

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/462 Primary

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title