Method of manufacturing an embedded printed circuit board

Patent metadata

Field	Value
Publication number	US-9265161-B2
Application number	US-95654510-A
Country	US
Kind code	B2
Filing date	Nov 30, 2010
Priority date	Nov 30, 2009
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

An embedded PCB, a multi-layer PCB using the embedded PCB, and a method of manufacturing the same are provided. The method of manufacturing an embedded PCB includes a first step of patterning an insulating layer on which a photoresist layer is formed using a laser such that parts of the insulating layer are selectively etched to form a circuit pattern region and a second step of filling the circuit pattern region with a plating material to form a circuit pattern. Accordingly, the method of manufacturing an embedded PCB can simultaneously or sequentially etch a photoresist layer and an insulating layer using a laser to form a circuit pattern so as to obtain a micro pattern and simplify a manufacturing process and achieve alignment accuracy in construction of a multi-layer PCB using the embedded PCB to thereby improve product reliability and yield.

First claim

What is claimed is:

1. A method of manufacturing an embedded printed circuit board (PCB), comprising:
a first step of laser-patterning an insulating layer and a photoresist layer laminated on the insulating layer together to form a circuit pattern region in which a part of the insulating layer is etched;
a second step of forming a metal seed layer on the insulating layer on which the circuit pattern region is formed, and filling the circuit pattern region with a metal material;
a third step of removing the metal seed layer from a top face of a circuit pattern so that the metal seed layer is formed on the remaining surface except for the top face of the circuit pattern, thereby forming a first printed circuit board; and
a fourth step of disposing the first printed circuit board on a first surface of an inner circuit board,
wherein the method further comprises: forming a second printed circuit board by the first through third steps; and disposing the second printed circuit board on a second surface of the inner circuit board opposite to the first surface.

2. The method of claim 1 , wherein the metal seed layer is formed of one or more of Cu, Au, Ni, Pd, In, Ti, Sn, and a conductive polymer.

3. The method of claim 1 , wherein the metal material includes at least one of Cu, Ag, Sn, Au, Ni and Pd.

4. The method of claim 1 , wherein the circuit pattern region is filled with the metal material using electroless plating, electroplating, screen printing, sputtering, evaporation, ink jetting, dispensing, or a combination thereof.

5. The method of claim 1 , wherein the insulating layer is composed of a carrier layer and an insulating member formed thereon.

Assignees

• Ahn Chi Hee
• Lee Sang Myung
• Seo Yeong Uk
• Kim Jin Su
• Yoon Sung Woon
• Nam Myoung Hwa
• Lg Innotek Co Ltd

Inventors

• Ahn Chi Hee
• Lee Sang Myung
• Seo Yeong Uk
• Kim Jin Su
• Yoon Sung Woon
• Nam Myoung Hwa

Classifications

• H05K3/4661

  Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387) · CPC title

• H05K3/0032

  of organic insulating material · CPC title

• H05K3/184

  using masks · CPC title

• Y10T29/49155

  Manufacturing circuit on or in base · CPC title

• H05K3/465 Primary

  by applying an insulating layer having channels for the next circuit layer · CPC title