Chip-to-chip communications

Patent metadata

Field	Value
Publication number	US-9264368-B2
Application number	US-201313752050-A
Country	US
Kind code	B2
Filing date	Jan 28, 2013
Priority date	Jan 27, 2012
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Devices and systems are described for transmitting data packets over a chip-to-chip communications link. For example, a device includes a hardware replay buffer to store a data packet. The data packet includes an overhead portion and a payload portion. Additionally, the transmitter device includes circuitry configured to record a memory location within the hardware replay buffer corresponding to an interruption in transmission to a receiver device of the payload portion of the data packet through a physical serial communications link. The memory location references an intermediate location of the payload portion of the data packet.

First claim

What is claimed is:

1. A transmitter device comprising:
a hardware replay buffer to store a data packet, wherein the data packet includes an overhead portion and a payload portion; and
circuitry configured to
transmit the overhead portion, to a receiver device, including one or more overhead bits indicating a total bit count of the payload portion to be received during transmission of the payload portion;
start the transmission of the payload portion to the receiver device through a physical serial communication link;
receive, from a host device and prior to completion of the transmission of the payload portion, a priority data packet having a higher priority than the data packet;
perform an interruption, before a transmission of the priority data packet, of the transmission of the payload portion in response to the receiving of the priority data packet, such that a remainder data of the payload portion in the hardware replay buffer remains to be transmitted upon resumption of the transmission of the payload portion;
record a memory location within the hardware replay buffer corresponding to the interruption, wherein the memory location references a first bit of the remainder data of the payload portion of the data packet;
transmit the priority data packet to the receiver device;
after the priority data packet has been transmitted, transmit another overhead portion, to the receiver device, including one or more overhead bits indicating a bit count of the remainder data of the payload portion to be received during resumed transmission of the payload portion; and

after transmission of the another overhead portion resume the transmission to the receiver device of the payload portion starting from the recorded memory location.

2. The transmitter device of claim 1 , wherein the memory location corresponding to the interruption comprises an offset into the hardware replay buffer indicating the first bit of the remainder data.

3. The transmitter device of claim 1 , wherein the circuitry comprises a register where the circuitry records the memory location corresponding to the interruption.

4. The transmitter device of claim 3 , wherein the register comprises a replay start location register, and the circuitry to record comprises a current transmission location register, the replay start location register, and an end of payload portion location register, and
is configured to transfer a value stored in the current transmission location register to the replay start register at a time of the interruption.

5. The transmitter device of claim 1 , wherein the circuitry transmits, to the receiver device immediately prior to resumption of the transmission of the payload portion, one or more overhead bits indicating to the receiver device that remainder data of the payload portion is to be received.

6. The transmitter device of claim 1 , wherein the circuitry is configured to
cause another interruption in transmission of a payload portion of another data packet in response to receipt of a message from the receiver device through a physical back communications link requesting the other interruption of the transmission of the payload portion of the other data packet;
record another memory location within the hardware replay buffer corresponding to the other interruption in the transmission to the receiver device of the payload portion of the other data packet through the physical serial communications link, wherein the other memory location references another intermediate location of the payload portion of the data packet; and
resumes the transmission of the payload portion of the other data packet after a predetermined time since the receipt of the message from the receiver.

7. A system comprising:
a physical communications link through which data packets are transmitted from a first integrated circuit (IC) device to a second IC device, wherein each of the data packets includes an overhead portion and a payload portion;
a transmitter to obtain a data packet from the first IC device and to transmit the data packet through the physical communications link; and
a receiver to receive the data packet transmitted through the physical communications link and to provide the data packet to the second IC device,
wherein the transmitter comprises
a hardware replay buffer to store the payload portion of the data packet during transmission of the data packet to the receiver through the physical communications link, and
transmitter circuitry configured to
transmit, to the receiver, the overhead portion including one or more overhead bits indicating a total bit count of the payload portion to be received during a transmission of the payload portion;
start the transmission of the payload portion;
receive, from a host device and prior to completion of the transmission of the payload portion, a priority data packet having a higher priority than the data packet;
perform an interruption, before a transmission of the priority data packet, of the transmission of the payload portion in response to the receiving of the priority data packet, such that a remainder data of the payload portion in the hardware replay buffer remains to be transmitted upon resumption of the transmission of the payload portion;
record a memory location within the hardware replay buffer corresponding to the interruption, where the memory location references a first bit of the remainder data of the payload portion;
transmit the priority data packet to the receiver device;
after the priority data packet has been transmitted, transmit another overhead portion, to the receiver device, including one or more overhead bits indicating a bit count of the remainder data of the payload portion to be received during resumed transmission of the payload portion; and
after the another overhead portion has been transmitted, resume the transmission to the receiver device of the payload portion starting from the recorded memory location, and

wherein the receiver comprises
a hardware receiver buffer to store the data packet transmitted through the physical communications link, and

receiver circuitry configured to count a quantity of bits received as part of the payload portion and to record the count.

8. The system of claim 7 , wherein the memory location corresponding to the interruption comprises an offset into the hardware replay buffer indicating the first bit of the remainder data.

9. The system of claim 7 , wherein the transmitter circuitry comprises a register where the transmitter circuitry records the memory location corresponding to the interruption.

10. The system of claim 7 , wherein the transmitter circuitry causes the interruption of the transmission of the payload portion once a predetermined fraction of the payload portion is transmitted through the physical communications link after receipt of an instruction requesting the interruption.

11. The system of claim 7 , wherein the transmitter comprises a second hardware replay buffer different from the hardware replay buffer to store a payload portion of the priority data packet during transmission of the priority data packet through the physical communications link,
the receiver comprises a second hardware receiver buffer different from the hardware receiver buffer to store the payload portion of the priority data packet during transmission of the priority data packet transmitted through the physical communications link,
the hardware receiver buffer and the second hardware receiver buffer are mapped to memory address space associated with the second IC device, and
the transmitter circuitry transmits, prior to the transmissions of the payload portions of the data packet and the pri

Assignees

• Marvell World Trade Ltd
• Marvell World Trade Ltd

Inventors

• Swarbrick Ian
• Cao Joseph Jun

Classifications

• H04L69/22

  Parsing or analysis of headers · CPC title

• G06F13/423 Primary

  with synchronous protocol · CPC title

• H04L47/24 Primary

  Traffic characterised by specific attributes, e.g. priority or QoS · CPC title

• H04L25/02

  Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} · CPC title

• H04L47/6215

  Individual queue per QOS, rate or priority · CPC title