Semiconductor device having interconnection line

Patent metadata

Field	Value
Publication number	US-9263576-B2
Application number	US-201414576257-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Jun 27, 2014
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an insulating layer extending in a first direction;
a first vertical channel pillar disposed separately from the insulating layer;
a first interconnection line extending in a second direction perpendicular to the first direction, wherein the first interconnection line is electrically connected to the first vertical channel pillar;
a first bit line extending in the second direction, wherein the first bit line crosses over the first interconnection line and the first vertical channel pillar; and
a first bit contact overlapping the first interconnection line, wherein the first bit contact electrically connects the first interconnection line to the first bit line, and
wherein a length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.

2. The semiconductor device of claim 1 , wherein the first bit contact includes a portion overlapping the insulating layer.

3. The semiconductor device of claim 2 , wherein the first bit contact crosses over the insulating layer.

4. The semiconductor device of claim 1 , wherein a length of the first interconnection line in the first direction is smaller than a diameter of the first vertical channel pillar.

5. The semiconductor device of claim 1 , further comprising:
a second vertical channel pillar disposed separately from the insulating layer and the first vertical channel pillar;
a second bit line disposed in parallel with the first bit line, wherein the second bit line crosses over the second vertical channel pillar; and
a second bit contact including a region on which the second bit line overlaps, wherein the second bit contact electrically connects the second vertical channel pillar to the second bit line, and
wherein a length of the second bit contact in the second direction is greater than a length of the second bit contact in the first direction.

6. The semiconductor device of claim 5 , wherein a shape of the second bit contact is the same as a shape of the first bit contact.

7. The semiconductor device of claim 5 , further comprising a second interconnection line disposed in parallel with the first interconnection line, wherein the second interconnection line electrically connects the second vertical channel pillar to the second bit contact, and wherein the second bit contact overlaps the second interconnection line.

8. The semiconductor device of claim 7 , wherein a length of the second interconnection line in the second direction is greater than a length of the first interconnection line in the second direction.

9. The semiconductor device of claim 7 , wherein a distance in the second direction between the first vertical channel pillar and the first bit contact is substantially the same as a distance in the second direction between the second vertical channel pillar and the second bit contact.

10. A semiconductor device, comprising:
a plurality of gate electrodes disposed on a semiconductor substrate;
a first vertical channel pillar penetrating the plurality of gate electrodes;
a first bit line disposed on the gate electrodes, wherein the first bit line crosses over the first vertical channel pillar;
an interconnection line disposed between the first vertical channel pillar and the first bit line, wherein the interconnection line extends along the first bit line; and
a first bit contact disposed between the interconnection line and the first bit line,
wherein a horizontal length of the first bit contact is greater than a horizontal length of the first vertical channel pillar.

11. The semiconductor device of claim 10 , further comprising:
a second vertical channel pillar penetrating the gate electrodes, wherein the second vertical channel pillar is spaced apart from the first vertical channel pillar;
a second bit line disposed on the gate electrodes, wherein the second bit line crosses over the second vertical channel pillar; and
a second bit contact disposed between the second vertical channel pillar and the second bit line.

12. The semiconductor device of claim 11 , wherein a horizontal length of the second bit contact is greater than a horizontal length of the second vertical channel pillar.

13. The semiconductor device of claim 11 , further comprising an interconnection contact disposed between the second vertical channel pillar and the second bit contact.

14. The semiconductor device of claim 13 , wherein a level of a lower surface of the second bit contact is the same as a level of a lower surface of the first bit contact.

15. The semiconductor device of claim 13 , wherein a level of a lower surface of the second bit contact is higher than a level of an upper surface of the interconnection line.

16. A semiconductor device, comprising:
a first vertical channel pillar comprising a first channel active pattern and a first channel core pattern;
a second vertical channel pillar comprising a second channel active region and a second channel core pattern, wherein the second vertical channel pillar is disposed separately from the first vertical channel pillar;
an insulating layer between the first vertical channel pillar and the second vertical channel pillar;
a first bit contact electrically connected to the first vertical channel pillar and a first bit line, wherein the first bit contact is disposed above the insulating layer;
a second bit contact electrically connected to the second vertical channel pillar and a second bit line, wherein the second bit contact is disposed above the second vertical channel pillar; and
an interconnection line electrically connected to the first vertical channel pillar and the first bit contact, wherein a first side of the interconnection line is parallel with a second side of the interconnection line opposite to the first side of the interconnection line.

17. The semiconductor device of claim 16 , wherein the first vertical channel pillar is closer to the insulating layer than the second vertical channel pillar.

18. The semiconductor device of claim 16 , wherein a length of the first bit contact is smaller than a length of the insulating layer.

19. The semiconductor device of claim 16 , wherein the first bit line and the second bit line are not in contact with each other.

20. The semiconductor device of claim 16 , further comprising an impurity region disposed on the substrate, wherein the impurity region is disposed under the insulating layer.

Assignees

• Yun Jang-Gn
• Cho Hoo-Sung
• Yun Jae-Sun
• Samsung Electronics Co Ltd

Inventors

• Yun Jang-Gn
• Cho Hoo-Sung
• Yun Jae-Sun

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic