Switching element with a series-connected junction FET (JFET) and MOSFET achieving both improved withstand voltage and reduced on-resistance

Patent metadata

Field	Value
Publication number	US-9263435-B2
Application number	US-201114348048-A
Country	US
Kind code	B2
Filing date	Sep 30, 2011
Priority date	Sep 30, 2011
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP 1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a junction FET (field-effect transistor) of a normally-on type formed of a substance having a band gap larger than that of silicon and having a first gate electrode, a first source, and a first drain; and
a MOSFET (metal-oxide semiconductor FET) of a normally-off type formed of silicon and having a second gate electrode, a second source, and a second drain,
the semiconductor device including a cascode connection in which the first source of the junction FET and the second drain of the MOSFET being electrically connected and the first gate electrode of the junction FET and the second source of the MOSFET being electrically connected, and
the semiconductor device comprising:
(a) a first semiconductor chip having a first front surface in which a first source pad electrically connected to the first source of the junction FET and a first gate pad electrically connected to the first gate electrode of the junction FET are formed and a first back surface electrically connected to the first drain of the junction FET and opposite to the first front surface;
(b) a second semiconductor chip having a second front surface in which a second source pad electrically connected to the second source of the MOSFET and a second gate pad electrically connected to the second gate electrode of the MOSFET are formed and a second back surface electrically connected to the second drain of the MOSFET and opposite to the second front surface;
(c) a first chip mount unit having a first upper surface on which the first semiconductor chip is mounted via a first conductive adhesive material;
(d) a drain lead coupled to the first chip mount unit;
(e) a source lead electrically insulated from the drain lead;
(f) a gate lead electrically insulated from the drain lead and the source lead;
(g) a first metal conductor for electrically connecting the first gate pad of the first semiconductor chip and the source lead together; and
(h) a sealing body which seals the first semiconductor chip, the second semiconductor chip, part of the first chip mount unit, part of the drain lead, part of the source lead, and part of the gate lead, and the first metal conductor,
wherein the first source pad of the first semiconductor chip and the second back surface of the second semiconductor chip are electrically connected together,
the second gate pad of the second semiconductor chip and the gate lead are electrically connected together,
the second source pad of the second semiconductor chip and the source lead are electrically connected together, and
the first gate pad of the first semiconductor chip are disposed so as to be closer to the source lead than to other leads.

2. The semiconductor device according to claim 1 ,
wherein the second gate pad of the second semiconductor chip and the gate lead are electrically connected together via a second metal conductor, and
the second gate pad of the second semiconductor chip is disposed so as to be closer to the gate lead than to the second source pad.

3. The semiconductor device according to claim 2 ,
wherein the first metal conductor has a conductor width wider than a conductor width of the second metal conductor.

4. The semiconductor device according to claim 2 ,
wherein the second semiconductor chip is mounted on the first source pad of the first semiconductor chip via a second conductive adhesive material so that the second back surface of the second semiconductor chip and the first source pad of the first semiconductor chip face each other.

5. The semiconductor device according to claim 4 ,
wherein the first semiconductor chip is disposed on the first chip mount unit so as to be closer to the source lead than to the other leads.

6. The semiconductor device according to claim 4 ,
wherein the second source pad of the second semiconductor chip and the source lead are electrically connected via a third metal conductor.

7. The semiconductor device according to claim 6 ,
wherein the first metal conductor, the second metal conductor, and the third metal conductor are bonding wires.

8. The semiconductor device according to claim 7 ,
wherein a plurality of the bonding wires of the third metal conductor are present.

9. The semiconductor device according to claim 4 ,
wherein the first conductive adhesive material and the second conductive adhesive material are either of silver paste or solder.

10. The semiconductor device according to claim 6 ,
wherein the source lead has a source lead post portion,
the gate lead has a gate lead post portion,
the first metal conductor and the third metal conductor are connected to the source lead post portion, and
the second metal conductor is connected to the gate lead post portion.

11. The semiconductor device according to claim 10 ,
wherein a region in which the first metal conductor and the third metal conductor of the source lead post portion are connected and a region in which the second metal conductor of the gate lead post portion is connected are placed at positions higher than the first upper surface of the first chip mount unit.

12. The semiconductor device according to claim 1 ,
wherein the sealing body has a first side surface and a second side surface facing the first side surface, and
the drain lead, the gate lead, and the source lead protrude from the first side surface of the sealing body.

13. The semiconductor device according to claim 12 ,
wherein the drain lead is disposed between the gate lead and the source lead.

14. The semiconductor device according to claim 1 ,
wherein the semiconductor device has a second upper surface on which the second semiconductor chip is mounted, and further includes a second chip mount unit electrically insulated from the first chip mount unit,
the second back surface of the second semiconductor chip and the second upper surface of the second chip mount unit are electrically connected together via a third conductive adhesive material, and
the first source pad of the first semiconductor chip and the second upper surface of the second chip mount unit are electrically connected together via a fourth metal conductor.

15. The semiconductor device according to claim 14 ,
wherein the fourth metal conductor is a bonding wire.

16. The semiconductor device according to claim 14 ,
wherein part of the sealing body is disposed between the first chip mount unit and the second chip mount unit.

17. The semiconductor device according to claim 1 ,
wherein the first chip mount unit further has a first lower surface opposite to the first upper surface, and
the first lower surface of the first chip mount unit is exposed from the sealing body.

18. The semiconductor device according to claim 1 ,
wherein the sealing body has a first side surface and a second side surface facing the first side surface,
the gate lead and the source lead protrude from the first side surface of the sealing body, and
the drain lead protrudes from the second side surface of the sealing body.

19. The semiconductor device according to claim 1 ,
wherein the first metal conductor is electrically connected also to the second source pad of the second semiconductor chip, and
the first metal conductor is a metal plate.

20. The semiconductor device according to claim 19 ,
wherein the metal plate is formed of a copper material.

21. The semiconductor device according to claim 1 ,
wherein the junction FET is made of silicon carbide.

Assignees

• Kanazawa Takamitsu
• Akiyama Satoru
• Renesas Electronics Corp

Inventors

• Kanazawa Takamitsu
• Akiyama Satoru

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/762

  between stacked chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title