Semiconductor device and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-9263374-B2
Application number	US-201113230128-A
Country	US
Kind code	B2
Filing date	Sep 12, 2011
Priority date	Sep 28, 2010
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a lead frame including a die pad and a plurality of leads each disposed around the die pad;
a semiconductor element rested on the die pad of the lead frame;
electroconductive portions for electrically interconnecting the lead of the lead frame and the semiconductor element; and
a sealing resin section for sealing the lead frame, the semiconductor element, and electroconductive portions;
wherein the sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region; and
thickness of the central region is greater than that of the marginal region, wherein:
each of the leads includes an external terminal exposed to the exterior, the external terminal is configured to be connected to an outside member of the semiconductor device;
the external terminals of the leads are disposed on at least two round lines including an inner round line and an outer round line, the external terminals are arranged in a staggered layout; and
the external terminals arranged on the inner round line have a smaller size than the external terminals arranged on the outer round line.

2. The semiconductor device according to claim 1 , wherein:
each of the leads has a band-like shape radially extending outward from the die pad side.

3. The semiconductor device according to claim 2 , wherein:
each of the leads includes two external terminals, one external lead as an upper terminal provided at an upper surface of the lead, and the other external lead as a lower terminal provided at a lower surface of the lead.

4. The semiconductor device according to claim 3 , wherein:
each lead has a stepped portion between an internal terminal of the lead and the lower terminal of the lead.

5. The semiconductor device according to claim 3 , wherein:
a solder ball is provided on at least one upper terminal of the leads.

6. The semiconductor device according to claim 3 , wherein:
a heatsink fin is mounted on at least one upper terminal of the leads.

7. The semiconductor device according to claim 3 , wherein:
an electronic component is mounted on at least one upper terminal of the leads.

8. The semiconductor device according to claim 1 , wherein:
each lead is exposed at an upper surface of the marginal region of the sealing resin section.

9. The semiconductor device according to claim 1 , wherein:
the central region of the sealing resin section has a truncated conical shape, a columnar shape, a polygonal columnar shape, a truncated polygonal pyramidal shape, or a dome-like shape.

10. The semiconductor device according to claim 1 , wherein:
the die pad is circular in a top view.

11. The semiconductor device according to claim 1 , wherein:
the die pad is circular in a bottom view.

12. The semiconductor device according to claim 10 , wherein:
upper and lower surfaces of the die pad have different shapes.

13. The semiconductor device according to claim 1 , wherein:
hanging leads each including an external terminal are connected to the die pad.

14. The semiconductor device according to claim 13 , wherein:
upper and lower surfaces of the hanging lead each have a recessed portion which the sealing resin section flows into, and layouts of the recessed portions of the upper and lower surfaces of the hanging lead differ from each other in a plane view.

15. The semiconductor device according to claim 1 , wherein:
a lower surface of the die pad is exposed to the exterior of the sealing resin section.

16. The semiconductor device according to claim 1 , wherein:
a lower surface of the die pad is not exposed to the exterior of the sealing resin section.

17. The semiconductor device according to claim 1 , wherein:
the level of an upper surface of the die pad is lower than the level of an upper surface of each lead.

18. The semiconductor device according to claim 1 , wherein:
a flange is provided along a rim of an upper surface of the die pad.

19. A semiconductor device comprising:
a lead frame including a die pad and a plurality of leads each disposed around the die pad;
a semiconductor element rested on the die pad of the lead frame;
electroconductive portions for electrically interconnecting the lead of the lead frame and the semiconductor element; and
a sealing resin section for sealing the lead frame, the semiconductor element, and electroconductive portions; wherein:
each of the leads includes an external terminal exposed at a lower surface of the sealing resin section, the external terminal is configured to be connected to an outside member of the semiconductor device, each external terminal of the lead is disposed on at least two round lines including an inner round line and an outer round line, and the external terminals are arranged in a staggered layout;
the die pad and the leads protrude downward from the sealing resin section; and
the external terminals arranged on the inner round line have a smaller size than the external terminals arranged on the outer round line.

20. A semiconductor device comprising:
a lead frame including a die pad and a plurality of leads each disposed around the die pad;
a semiconductor element rested on the die pad of the lead frame;
electroconductive portions for electrically interconnecting the lead of the lead frame and the semiconductor element; and
a sealing resin section for sealing the lead frame, the semiconductor element, and electroconductive portions; wherein:
each of the leads includes external terminal exposed to the exterior of the sealing resin section, the external terminal is configured to be connected to an outside member of the semiconductor device
each external terminal of the lead is disposed on at least two round lines including an inner round line and an outer round line, the external terminals are arranged in a staggered layout; and
the external terminals arranged on the inner round line have a smaller size than the external terminals arranged on the outer round line.

21. A semiconductor device comprising:
a semiconductor element;
a plated portion for semiconductor element placement on which the semiconductor element is rested;
a plurality of plated portions for leads disposed around the plated portion for semiconductor element placement and on the same plane as the plated portion for semiconductor element placement, each of the plated portions for leads is configured to be connected to an outside member of the semiconductor device;
electroconductive portions for electrically interconnecting one of the plated portions for leads and the semiconductor element; and
a sealing resin section for sealing the plated portion for semiconductor element placement, the plated portions for leads, the semiconductor element, and the electroconductive portions; wherein:
the plated portions for leads are disposed on at least two round lines including an inner round line and an outer round line, the plated portions for leads are arranged in a staggered layout; and
the plated portions for leads arranged on the inner round line have a smaller size than the plated portions for leads arranged on the outer round line.

22. A semiconductor device comprising:
a non-electroconductive substrate;
a semiconductor element-mounting section provided at an upper-surface of the non-electroconductive substrate;
internal terminals disposed around the semiconductor element-mounti

Assignees

• Masuda Masachika
• Tomita Koji
• Okamoto Tadashi
• Tanaka Yasunori
• Ohsawa Hiroshi
• Miyano Kazuyuki
• Kurahashi Atsushi
• Suzuki Hiromichi
• Dainippon Printing Co Ltd

Inventors

• Masuda Masachika
• Tomita Koji
• Okamoto Tadashi
• Tanaka Yasunori
• Ohsawa Hiroshi
• Miyano Kazuyuki
• Kurahashi Atsushi
• Suzuki Hiromichi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/40

  Leadframes · CPC title