Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Method of forming semiconductor device
US9263294B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9263294-B2 |
| Application number | US-201414273283-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 8, 2014 |
| Priority date | May 8, 2014 |
| Publication date | Feb 16, 2016 |
| Grant date | Feb 16, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor device, comprising: forming a material layer on a substrate; forming a first flowing material layer on the material layer; forming a first mask layer on the first flowing material layer; performing a first etching process by using the first mask layer as a mask, so as to form a first opening in the material layer; removing the first mask layer and the first flowing material layer; forming a filler layer in the fi…
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Classifications
Electricity · mapped topic
- H10P50/73Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P50/283Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9263294B2 cover?
- A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P50/73. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).