Flash memory structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9263293-B2
Application number	US-201414152162-A
Country	US
Kind code	B2
Filing date	Jan 10, 2014
Priority date	Jan 10, 2014
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Embodiments of mechanisms of a semiconductor structure are provided. The semiconductor device structure includes a substrate and a floating gate having a first sidewall and a second sidewall formed over the substrate. The semiconductor device further includes an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate. The semiconductor device further includes a control gate formed over the insulating layer. In addition, the floating gate is formed in a shark's fin shape.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a floating gate having a first sidewall and a second sidewall formed over the substrate;
an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate;
a control gate formed over the insulating layer;
a first spacer formed on a first sidewall of the control gate over the floating gate, wherein a bottom surface of the first spacer directly contacts the second sidewall of the floating gate; and
a second spacer formed on a second sidewall of the control gate,
wherein the floating gate is formed in a shark's fin shape, and a top surface of the control gate connecting the first sidewall and the second sidewall of the control gate has a step-like profile.

2. The semiconductor structure as claimed in claim 1 , wherein an angle between the first sidewall and the second sidewall of the floating gate is in a range from about 30° to about 60°.

3. The semiconductor structure as claimed in claim 1 , wherein an angle between the second sidewall and a bottom surface of the floating gate is in a range from about 30° to about 60°.

4. The semiconductor structure as claimed in claim 1 , wherein the insulating layer directly contacts the upper portion of the second sidewall of the floating gate.

5. The semiconductor structure as claimed in claim 1 , wherein the floating gate has a first height and a first width, and a ratio of the first height to the first width is in a range from about 0.5 to about 2.

6. The semiconductor device structure as claimed in claim 1 , wherein the insulating layer has a thickness in a range from about 100 Å to about 300 Å.

7. The semiconductor device structure as claimed in claim 1 , wherein the floating gate is a triangle floating gate having a tip structure.

8. The semiconductor device structure as claimed in claim 1 , wherein the floating gate has a tip structure.

9. A semiconductor structure, comprising:
a substrate;
a floating gate having a first sidewall and a second sidewall formed over the substrate;
an insulating layer covering the first sidewall and an upper portion of the second sidewall of the floating gate;
a control gate formed over the insulating layer;
a first spacer formed on a first sidewall of the control gate over the floating gate, wherein a bottom surface of the spacer directly contacts the second sidewall of the floating gate; and
a second spacer formed on a second sidewall of the control gate,
wherein an angle between the first sidewall and the second sidewall of the floating gate is in a range from about 30° to about 60°, and a top surface of the control gate connecting the first sidewall and the second sidewall of the control gate has a step-like profile.

10. The semiconductor structure as claimed in claim 9 , wherein the floating gate is formed in a shark's fin shape.

11. The semiconductor structure as claimed in claim 9 , wherein an angle between the second sidewall and a bottom surface of the floating gate is in a range from about 30° to about 60°.

12. The semiconductor structure as claimed in claim 9 , wherein the insulating layer directly contacts the upper portion of the second sidewall of the floating gate.

13. The semiconductor structure as claimed in claim 9 , wherein the floating gate has a first height and a first width, and a ratio of the first height to the first width is in a range from about 0.5 to about 2.

14. The semiconductor device structure as claimed in claim 9 , wherein the insulating layer has a thickness in a range from about 100 Å to about 300 Å.

15. The semiconductor device structure as claimed in claim 9 , wherein the floating gate is a triangle floating gate.

16. The semiconductor device structure as claimed in claim 15 , wherein the triangle floating gate has a tip structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Yu-Ling

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P50/283 Primary

  by chemical means · CPC title