High-k/metal gate transistor with L-shaped gate encapsulation layer

Patent metadata

Field	Value
Publication number	US-9263276-B2
Application number	US-55129209-A
Country	US
Kind code	B2
Filing date	Nov 18, 2009
Priority date	Nov 18, 2009
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

First claim

What is claimed is:

1. A method for fabricating a transistor, the method comprising:
providing a silicon layer above a substrate, the silicon layer being separated from the substrate by one or more layers;
forming a first layer on and in contact with the silicon layer, the first layer comprising a high dielectric constant material;
forming a second layer and in contact with the first layer, the second layer comprising a metal or metal alloy;
forming a third layer on the second layer, the third layer comprising silicon or polysilicon;
etching the first, second, and third layers so as to form first, second, and third layers of a gate stack;
depositing an encapsulation layer, the encapsulation layer including a horizontal portion in contact with the silicon layer and a vertical portion that is located on and in contact with sidewalls of the gate stack;
after depositing the encapsulation layer, depositing one spacer layer above and in contact with the horizontal portion of the encapsulation layer and adjacent to and in contact with the vertical portion of the encapsulation layer,
wherein depositing the one spacer layer comprises
depositing a first spacer layer above the horizontal portion of the encapsulation layer and adjacent to the vertical portion of the encapsulation layer, and
after depositing the first spacer layer, depositing a second spacer layer;

after depositing the spacer layer, etching the encapsulation layer and the one spacer layer so as to form a spacer and an L-shaped gate encapsulation layer that is disposed on the sidewalls of the gate stack, the L-shaped gate encapsulation layer comprising a vertical portion covering and in contact with the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering and in contact with a portion of the silicon layer that is adjacent to the gate stack, and the spacer being above and in contact with the horizontal portion of the L-shaped gate encapsulation layer and adjacent to and in contact with the vertical portion of the L-shaped gate encapsulation layer, the spacer extending from the vertical portion of the L-shaped gate encapsulation layer to the horizontal portion of the L-shaped gate encapsulation layer, the spacer comprising a vertical sidewall extending from a surface of the horizontal portion of the L-shaped gate encapsulation layer to a height above at least the second layer comprising the metal or metal alloy,
wherein etching the encapsulation layer and the at least one spacer layer further comprises
etching the first spacer layer and the second spacer layer so as to form the spacer, the spacer further comprising:
an L-shaped spacer layer that includes a vertical portion covering sidewalls of the vertical portion of the L-shaped gate encapsulation layer, and a horizontal portion covering the horizontal portion of the L-shaped gate encapsulation layer, where the L-shaped spacer layer is formed with a thickness that is less than a thickness of the L-shaped gate encapsulation layer; and
the second spacer layer disposed on sidewalls of the vertical portion of the L-shaped oxide layer and above the horizontal portion of the L-shaped oxide layer, wherein the L-shaped gate encapsulation layer, the L-shaped spacer layer, and the second spacer layer are formed with a combined width that is greater than a width of the gate stack;

after etching the encapsulation layer and the one spacer layer, performing an extension implantation to implant ions so as to form source/drain extensions in the silicon layer, the source/drain extensions not underlying the gate stack; and
after performing the extension implantation, performing a source/drain implantation and performing an anneal to implant and diffuse ions for source and drain regions in the silicon layer,
wherein the extension implantation and the source/drain implantation are two separate implantations, and
both the extension implantation and the source/drain implantation are performed after etching the encapsulation layer and the one spacer layer and while the spacer is present above the horizontal portion of the L-shaped gate encapsulation layer and adjacent to the vertical portion of the L-shaped gate encapsulation layer.

2. The method of claim 1 , wherein a thickness of the L-shaped gate encapsulation layer is less than a thickness of the first layer of the gate stack.

3. The method of claim 1 , wherein a thickness of the vertical portion of the L-shaped gate encapsulation layer is substantially equal to a thickness of the horizontal portion of the L-shaped gate encapsulation layer.

4. The method of claim 1 , wherein depositing the encapsulation layer comprises performing molecular layer deposition (MLD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or rapid thermal chemical vapor deposition (RTCVD) to deposit a layer of nitride.

5. The method of claim 1 , wherein the first spacer layer is an oxide layer, and where the second spacer layer is a nitride layer.

6. The method of claim 1 , wherein the horizontal portion of the L-shaped gate encapsulation layer directly contacts the silicon layer.

7. The method of claim 1 , wherein depositing an encapsulation layer is performed after etching the first, second, and third layers.

8. The method of claim 1 , wherein portions of the source and drain regions underlie the spacer.

9. The method of claim 1 , wherein etching the first, second, and third layers comprises performing a single etch that etches the first, second, and third layers and stops on the silicon layer, so as to form the gate stack in the single etch.

10. The method of claim 1 , wherein the L-shaped gate encapsulation layer consists of a single layer.

11. The method of claim 1 ,
wherein the L-shaped gate encapsulation layer consists of a single encapsulation layer, the spacer consists of a single spacer layer, and
the single spacer layer of the spacer directly contacts the single encapsulation layer of the L-shaped gate encapsulation layer.

12. The method of claim 1 ,
wherein
the first spacer layer consists of SiO2.

13. The method of claim 1 ,
wherein
the first spacer layer does not comprise a high dielectric constant material and the second spacer layer comprises a nitride layer.

14. A non-transitory computer readable storage medium encoded with a program for fabricating a nFET transistor and a pFET transistor, the program comprising instructions for performing:
providing a buried oxide layer on and in contact with a single substrate, where the single substrate comprises an nFET region and a pFET region;
providing a silicon layer on and in contact with the buried oxide layer, the silicon layer being provided across both the nFET and pFET regions of the substrate;
depositing a silicon germanium layer on and in contact with the silicon layer;
forming a first layer on and in contact with the silicon germanium layer, the first layer comprising a high dielectric constant material, the first layer being provided across both the nFET and pFET regions of the substrate;
forming a second layer on and in contact with the first layer, the second layer comprising a metal or metal alloy and being provided across both the nFET and pFET regions of the substrate;
forming a third layer on the second layer, the third layer comprising silicon or polysilicon and being provided across both the nFET and pFET regions of the substrate;
etching the first, second, and third layers so as to form first, second, and third layers of a first gate stack in the nFET region and first, second, and third layers of a second gate stack in the pFET region;
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Assignees

• Mo Renee T
• Natzle Wesley C
• Narayanan Vijay
• Sleight Jeffrey W
• IBM

Inventors

• Mo Renee T
• Natzle Wesley C
• Narayanan Vijay
• Sleight Jeffrey W

Classifications

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title