Nonplanar iii-n transistors with compositionally graded semiconductor channels
US-2016293774-A1 · Oct 6, 2016 · US
Method for selective growth of highly doped group IV—Sn semiconductor materials
US9263263B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9263263-B2 |
| Application number | US-201313944592-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 17, 2013 |
| Priority date | Jul 17, 2012 |
| Publication date | Feb 16, 2016 |
| Grant date | Feb 16, 2016 |
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Abstract
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Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method comprising: providing a patterned substrate comprising at least a first region and a second region, wherein the first region comprises an exposed first semiconductor material and the second region comprises an exposed insulator material; and performing at least two cycles of a grow-etch cyclic process, wherein each cycle comprises: (i) depositing a doped Group IV-Tin (Sn) layer, wherein a Sn concentration throughout the doped Group IV-Sn la…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9263263B2 cover?
- Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cycli…
- Who is the assignee on this patent?
- Imec
- What technology area does this patent fall under?
- Primary CPC classification H10P14/2907. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).