Method and device for evaluating a chip manufacturing process

Patent metadata

Field	Value
Publication number	US-9263154-B2
Application number	US-201414335972-A
Country	US
Kind code	B2
Filing date	Jul 21, 2014
Priority date	Jul 21, 2014
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.

First claim

What is claimed is:

1. A method for evaluating a chip manufacturing process comprising:
measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip;
determining a distribution of bit failure rates from the measured bit failure rates;
determining a maximum allowed bit failure rate from a given chip failure rate limit;
determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate; and
determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.

2. The method according to claim 1 , further comprising adapting the chip manufacturing process if the chip manufacturing process is not suitable for the chip failure rate limit.

3. The method according to claim 1 , wherein determining whether the chip manufacturing process is suitable for the chip failure rate limit comprises determining whether the chip failure rate limit can be met with chips manufactured by means of the chip manufacturing process.

4. The method according to claim 1 , wherein the chips are memory chips and the bit failure rate of a chip is a failure rate of bits of the memory of the chip.

5. The method according to claim 1 , wherein the chips are memory chips and the bit failure rate of a chip is a failure rate of bits of the memory of the chip due to a predetermined failure mechanism.

6. The method according to claim 1 , wherein determining whether the chip manufacturing process is suitable for the chip failure rate limit comprises comparing the value with a predetermined threshold.

7. The method according to claim 6 , wherein the chip manufacturing process is determined to be suitable for the chip failure rate limit if the value is above the threshold.

8. The method according to claim 1 , wherein determining the distribution of bit failure rates from the measured bit failure rates comprises determining a log normal distribution of bit failure rates from the measured bit failure rates.

9. The method according to claim 8 , comprising determining the value based on a mean value of the determined log normal distribution.

10. The method according to claim 8 , comprising determining the value based on a standard deviation of the determined log normal distribution.

11. The method according to claim 1 , wherein the value is a process capability index.

12. The method according to claim 1 , wherein the value is a one-sided process capability index.

13. The method according to claim 1 , further comprising determining the number of chips in the plurality of chips based on a predetermined confidence level.

14. A device for evaluating a chip manufacturing process comprising:
a measuring arrangement configured to measure, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip; and
a processor configured to
determine a distribution of bit failure rates from the measured bit failure rates;
determine a maximum allowed bit failure rate from a given chip failure rate limit;
determine a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate; and
determine, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.

Assignees

• Infineon Technologies Ag

Inventors

• Tempel Georg

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G11C29/56008

  Error analysis, representation of errors · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C2029/0403

  during or with feedback to manufacture · CPC title

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title