Method and apparatus for concurrent test of flash memory cores

US9263147B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9263147-B2
Application numberUS-201414490170-A
CountryUS
Kind codeB2
Filing dateSep 18, 2014
Priority dateMay 8, 2014
Publication dateFeb 16, 2016
Grant dateFeb 16, 2016

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Abstract

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An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.

First claim

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What is claimed is: 1. An apparatus for concurrent test of a set of flash memory banks, comprising: a memory data path module coupled to a test controller, the test controller being configured to generate a test stimulus and to check a response from the set of flash memory banks, the memory data path module comprising: a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; a set of com…

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What does patent US9263147B2 cover?
An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response t…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification G11C29/26. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).