Systems and methods for dynamically programming a flash memory device

Patent metadata

Field	Value
Publication number	US-9263138-B1
Application number	US-201414502283-A
Country	US
Kind code	B1
Filing date	Sep 30, 2014
Priority date	Sep 30, 2014
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

The present inventions are related to systems and methods for storing data, and more particularly to systems and methods for writing data to a storage device.

First claim

What is claimed is:

1. A system for accessing a flash memory device, the system comprising:
a flash memory write circuit operable to apply a first write signal to a flash memory to yield a stored data set;
a flash memory read circuit operable to read the stored data set from the flash memory as a read back input;
a read back degrade circuit operable to degrade the read back input to yield a degraded output;
a data decoder circuit operable to apply a data decoding algorithm to the degraded output to yield a decoded output and a bit error rate; and
wherein the flash memory write circuit is further operable to apply a second write signal to the flash memory when the bit error rate exceeds a threshold value.

2. The system of claim 1 , wherein the data decoder circuit is selected from a group consisting of: a low density parity check decoder circuit operable to apply a low density parity check decoder algorithm to the degraded output to yield the decoded output and the bit error rate, and a comparator circuit operable to compare the degraded output to the stored data set to yield a number of bit errors as the bit error rate.

3. The system of claim 1 , wherein the threshold value is dynamic.

4. The system of claim 3 , wherein the threshold value is set at a first threshold level when the flash memory has been accessed a first number of times, and wherein the threshold value is set at a second threshold level when the flash memory has been accessed a second number of times.

5. The system of claim 1 , wherein the threshold value is user programmable.

6. The system of claim 1 , wherein the read back degrade circuit comprises:
a read threshold modification circuit operable to modify a read threshold of the flash memory read circuit to produce the degraded output.

7. The system of claim 6 , wherein the read threshold is modified such that the degraded output corresponds to the stored data set after a defined amount of time in the flash memory.

8. The system of claim 1 , wherein the read back degrade circuit comprises:
a bit erase circuit operable to modify a selected number of bits in the stored data set to correspond to an erase state of the flash memory device.

9. The system of claim 1 , wherein the system is implemented as part of an integrated circuit.

10. A system for accessing a flash memory device, the system comprising:
a flash memory write circuit operable to apply a first write signal to a flash memory to yield a stored data set;
a flash memory read circuit operable to read the stored data set from the flash memory as a read back input;
a low density parity check data decoder circuit operable to apply a low density parity check data decoding algorithm to a decoder input derived from the read back input to yield a decoded output; and
wherein the flash memory write circuit is further operable to selectively apply a second write signal to the flash memory based at least in part on the decoded output.

11. The system of claim 10 , wherein the system further comprises:
a read back degrade circuit operable to degrade the read back input to yield a degraded output, wherein the decoder input is derived from the degraded output.

12. The system of claim 11 , wherein the low density parity check data decoder circuit is further operable to yield a bit error rate associated with the decoded output, and wherein the flash memory write circuit is further operable to apply a second write signal to the flash memory based at least in part on the bit error rate.

13. The system of claim 10 , wherein selective application of the a second write signal to the flash memory is based upon a comparison of a bit error rate with a threshold value, wherein the bit error rate is derived from the decoded output, and wherein the threshold value is dynamic.

14. The system of claim 13 , wherein the threshold value is set at a first threshold level when the flash memory has been accessed a first number of times, and wherein the threshold value is set at a second threshold level when the flash memory has been accessed a second number of times.

15. The system of claim 11 , wherein the read back degrade circuit comprises:
a read threshold modification circuit operable to modify a read threshold of the flash memory read circuit to produce the degraded output.

16. The system of claim 15 , wherein the read threshold is modified such that the degraded output corresponds to the stored data set after a defined amount of time in the flash memory.

17. The system of claim 11 , wherein the read back degrade circuit comprises:
a bit erase circuit operable to modify a selected number of bits in the stored data set to correspond to an erase state of the flash memory device.

18. The system of claim 10 , wherein the system is implemented as part of an integrated circuit.

19. A system for accessing a flash memory device, the system comprising:
an auxiliary parity generation circuit operable to generate an additional parity data for a write data set;
a flash memory write circuit operable to apply a first write signal corresponding to the write data set to a flash memory to yield a stored data set;
a flash memory read circuit operable to read the stored data set from the flash memory;
a data decoder circuit operable to apply a data decoding algorithm to the read data to determine if the decoding fails to converge; and
wherein the flash memory write circuit is further operable to write a portion of the additional parity only if the decoding fails to converge.

20. The system of claim 19 , wherein the system is implemented as part of an integrated circuit.

Assignees

• Avago Technologies General Ip
• Seagate Technology

Inventors

• Wilson Bruce A
• Haratsch Erich F

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C16/12 Primary

  Programming voltage switching circuits · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title