Dynamic bank mode addressing for memory access

Patent metadata

Field	Value
Publication number	US-9262174-B2
Application number	US-201213440945-A
Country	US
Kind code	B2
Filing date	Apr 5, 2012
Priority date	Apr 5, 2012
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses.

First claim

The invention claimed is:

1. A method for accessing a multi-bank memory, the method comprising:
receiving a first memory access instruction included in a plurality of memory access instructions, wherein a bank mode is concurrently specified for each memory access instruction in the plurality of memory access instructions, and the first memory access instruction specifies an individual memory address;
receiving a bank mode that defines a per-bank bit-width for the first memory access instruction, wherein the bank mode specifies a first memory address-to-bank mapping when the bank mode is a first value and a second memory address-to-bank mapping when the bank mode is a second value;
dynamically mapping the individual memory address based on the bank mode to produce a mapped individual memory address; and
transmitting a read request or a write request to the multi-bank memory to execute the first memory access instruction.

2. The method of claim 1 , wherein
the first memory access instruction is for parallel execution by a first thread and additional threads in a first thread group,
the individual memory address is specified for the first thread in the thread group,
the first memory access instruction specifies additional individual memory addresses, including an individual memory address for each additional thread in the first thread group, and
the per-bank bit-width is associated with the first thread group; and
further comprising, dynamically mapping the individual memory address and the additional individual memory addresses based on the bank mode to produce a mapped individual memory address for the first thread and each additional thread in the first thread group.

3. The method of claim 2 , wherein a first mapped individual memory address for the first thread in the first thread group and a second mapped individual memory address for a second thread in the first thread group both map to a first bank of the multi-bank memory.

4. The method of claim 3 , wherein the first mapped individual memory address is included in the read request or the write request transmitted to the multi-bank memory during a first access cycle and the second mapped individual memory address is included in a second read or a second write request transmitted to the multi-bank memory during a second access cycle.

5. The method of claim 2 , further comprising:
receiving an active mask for the first thread group that indicates threads in the first thread group that should execute the first memory access instruction; and
determining that a bank conflict does not exist within the first thread group when a first mapped individual memory address for the first thread that is active and a second mapped individual memory address for a second thread that is not active both map to a first bank of the multi-bank memory.

6. The method of claim 2 , wherein the individual memory address and the additional memory addresses are each mapped to a different bank of the multi-bank memory for the per-bank bit-width and for a second per-bank bit-width and a number of bits access in each bank of the multi-bank memory is different for the bank mode compared with a different bank mode.

7. The method of claim 1 , further comprising:
receiving a second memory access instruction that specifies a second individual memory address;
receiving a second bank mode that defines a second per-bank bit-width;
dynamically mapping the second individual memory address based on the second bank mode to produce a second mapped individual memory address; and
transmitting a second read or a second write request to the multi-bank memory to execute the second memory access instruction for the second mapped individual memory address.

8. The method of claim 1 , wherein the per-bank bit-width is 32 and a second per-bank bit-width is 64.

9. The method of claim 1 , wherein the per-bank bit-width is 64 and a second per-bank bit-width is 128.

10. The method of claim 1 , wherein an N×M array of data is stored in the multi-bank memory and the first memory access instruction reads or writes either a column or a row of the N×M array without incurring a bank conflict.

11. The method of claim 1 , wherein the bank mode is specified to access data stored in each bank of the multi-bank memory without incurring a bank conflict when each bank of the multi-bank memory is N times the per-bank bit-width.

12. The method of claim 1 , wherein the bank mode further specifies a legacy bank mode corresponding to a different per-bank bit-width than the per-bank bit-width of the multi-bank memory.

13. The method of claim 1 , wherein the bank mode further specifies a first fill pattern of pad words when the bank mode is the first value and a second fill pattern of pad words when the bank mode is the second value.

14. A processing subsystem comprising:
an address generation unit that is configured to:
receive a first memory access instruction included in a plurality of memory access instructions, wherein a bank mode is concurrently specified for each memory access instruction in the plurality of memory access instructions, and the first memory access instruction specifies an individual memory address,
receive a bank mode that defines a per-bank bit-width for the first memory access instruction, wherein the bank mode specifies a first memory address-to-bank mapping when the bank mode is a first value and a second memory address-to-bank mapping when the bank mode is a second value, and
dynamically map the individual memory address based on the bank mode to produce a mapped individual memory address; and

a load/store unit coupled between the address generation unit and a multi-bank memory and configured to transmit a read request or a write request to the multi-bank memory to execute the first memory access instruction.

15. The processing subsystem of claim 14 , wherein
the first memory access instruction is for parallel execution by a first thread and additional threads in a first thread group,
the individual memory address is specified for the first thread in the thread group,
the first memory access instruction specifies additional individual memory addresses, including an individual memory address for each additional thread in the first thread group, and
the per-bank bit-width is associated with the first thread group; and the address generation unit is further configured to dynamically map the individual memory address and the additional individual memory addresses based on the bank mode to produce a mapped individual memory address for the first thread and each additional thread in the first thread group.

16. The processing subsystem of claim 15 , wherein a first mapped individual memory address for the first thread in the first thread group and a second mapped individual memory address for a second thread in the first thread group both map to a first bank of the multi-bank memory.

17. The processing subsystem of claim 16 , wherein the first mapped individual memory address is included in the read request or the write request transmitted to the multi-bank memory during a first access cycle and the second mapped individual memory address is included in a second read request or a second write request transmitted to the multi-bank memory during a second access cycle.

18. The processing subsystem of claim 15 , wherein the address generation unit is further configured to:
receive an active mask for the first thread group that indicates threads in the first thread group that should execute the first memory access instruction; and
determi

Assignees

• Fetterman Michael
• Carlton Stewart Glenn
• Hahn Douglas J
• Selvanesan Rajeshwaran
• Gadre Shirish
• Heinrich Steven James
• Nvidia Corp

Inventors

• Fetterman Michael
• Carlton Stewart Glenn
• Hahn Douglas J
• Selvanesan Rajeshwaran
• Gadre Shirish
• Heinrich Steven James

Classifications

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3887 Primary

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/38885

  Divergence aspects · CPC title