Real time instruction trace processors, methods, and systems

Patent metadata

Field	Value
Publication number	US-9262163-B2
Application number	US-201213730834-A
Country	US
Kind code	B2
Filing date	Dec 29, 2012
Priority date	Dec 29, 2012
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

First claim

What is claimed is:

1. A processor comprising:
at least a first logical processor; and
real time instruction trace (RTIT) logic coupled with the first logical processor, the RTIT logic including:
RTIT packetizer logic to generate RTIT packets for the first logical processor, the RTIT packets to indicate a flow of software executed by the first logical processor;
an RTIT queue corresponding to the first logical processor, the RTIT queue coupled with the RTIT packetizer logic, the RTIT queue to store the RTIT packets; and
RTIT queue contents transfer logic coupled with the RTIT queue, the RTIT queue contents transfer logic to transfer the RTIT packets to memory, wherein the RTIT queue contents transfer logic is implemented predominantly in firmware.

2. The processor of claim 1 , wherein the RTIT queue contents transfer logic comprises a firmware service sub-routine.

3. The processor of claim 1 , wherein the RTIT queue contents transfer logic is to transfer the RTIT packets to a set of architectural registers and then transfer the RTIT packets from the set of architectural registers to the memory through a store operation.

4. The processor of claim 3 , wherein the store operation comprises one selected from an uncacheable speculative write combining operation and a cacheable store operation.

5. The processor of claim 1 , wherein at least a portion of the RTIT queue is capable of being configured as a last branch record (LBR).

6. The processor of claim 1 , further comprising a non-renamed bus coupled with the RTIT packetizer logic, the non-renamed bus having a width in bits that is at least as large as a width of a line of the RTIT queue.

7. The processor of claim 1 , wherein a size of the RTIT queue ranges from 0.3 to 4 kilobytes corresponding to the first logical processor.

8. The processor of claim 7 , wherein the size of the RTIT queue ranges from 0.4 to 4 kilobytes corresponding to the first logical processor.

9. The processor of claim 1 , wherein the RTIT packetizer logic is implemented predominantly in hardware.

10. The processor of claim 1 , wherein the RTIT packetizer logic is to perform an intermediate level of compression in which non-operations (NOPs) are left between RTIT packets in the RRQ.

11. The processor of claim 1 , wherein the RTIT packetizer logic is to store packets of a given type in fixed locations of chunks.

12. The processor of claim 1 , wherein the RTIT logic is to provide a level of intrusiveness that ranges from 2% to 20% for the first logical processor.

13. A method comprising:
generating real time instruction trace (RTIT) packets for a first logical processor of a processor, the RTIT packets to indicate a flow of software executed by the first logical processor;
storing the RTIT packets in an RTIT queue corresponding to the first logical processor; and
transferring the RTIT packets from the RTIT queue to memory with predominantly firmware of the processor.

14. The method of claim 13 , wherein transferring comprises transferring the RTIT packets with a firmware service sub-routine.

15. The method of claim 13 , wherein transferring comprises:
transferring the RTIT packets from the RTIT queue to a set of architectural registers; and
transferring the RTIT packets from the set of architectural registers to the memory through a store operation.

16. The method of claim 15 , wherein transferring comprises transferring the RTIT packets from the set of architectural registers to the memory through a store operation selected from an uncacheable speculative write combining operation and a cacheable store operation.

17. The method of claim 13 , further comprising using at least a portion of the RTIT queue as a last branch record (LBR).

18. The method of claim 13 , further comprising transmitting a line of the RTIT queue on a non-renamed bus having a width in bits that is at least as wide as a width of the line of the RTIT queue.

19. The method of claim 13 , wherein storing comprises storing the RTIT packets in an RTIT queue having a size that ranges from 0.3 to 4 kilobytes corresponding to the first logical processor.

20. The method of claim 19 , wherein the size of the RTIT queue ranges from 0.4 to 4 kilobytes corresponding to the first logical processor.

21. The method of claim 13 , wherein generating the RTIT packets is performed predominantly by hardware of the processor.

22. The method of claim 13 , wherein storing the RTIT packets in the RTIT queue leaves non-operations (NOPs) between RTIT packets.

23. The method of claim 13 , further comprising providing a level of intrusiveness of RTIT that ranges from 2% to 20% for the first logical processor.

24. A system comprising:
an interconnect;
a dynamic random access memory (DRAM) coupled with the interconnect; and
a processor coupled with the interconnect, the processor including:
at least a first logical processor; and
real time instruction trace (RTIT) logic coupled with the first logical processor, the RTIT logic including:
RTIT packetizer logic to generate RTIT packets for the first logical processor, the RTIT packets to indicate a flow of software executed by the first logical processor;
an RTIT queue corresponding to the first logical processor, the RTIT queue coupled with the RTIT packetizer logic, the RTIT queue to store the RTIT packets; and
RTIT queue contents transfer logic coupled with the RTIT queue, the RTIT queue contents transfer logic to transfer the RTIT packets to the DRAM, wherein the RTIT queue contents transfer logic is implemented predominantly in fin ware of the processor.

25. The system of claim 24 , wherein the RTIT queue contents transfer logic comprises a firmware service sub-routine, and wherein the RTIT queue contents transfer logic is to transfer the RTIT packets to a set of architectural registers and then transfer the RTIT packets from the set of architectural registers to the DRAM through a store operation.

26. The system of claim 24 , wherein at least a portion of the RTIT queue is capable of being configured as a last branch record (LBR), and further comprising a non-renamed bus coupled with the RTIT packetizer logic, the non-renamed bus having a width in bits that is at least as large as a width of a line of the RTIT queue.

27. A processor comprising:
a real time instruction trace (RTIT) queue to store RTIT packets for a first logical processor, the RTIT packets to indicate a flow of software executed by the first logical processor; and
RTIT queue contents transfer logic coupled with the RTIT queue, the RTIT queue contents transfer logic to:
transfer the RTIT packets from the RTIT queue to a set of architectural registers; and
transfer the RTIT packets from the set of architectural registers to memory through a store operation.

28. The processor of claim 27 , wherein the RTIT queue contents transfer logic comprises a firmware service sub-routine.

29. The processor of claim 27 , wherein at least a portion of the RTIT queue is capable of being configured as a last branch record (LBR).

Assignees

• Intel Corp

Inventors

• Kurts Tsvika
• Levy Ofer
• Kazachinsky Itamar
• Malka Gabi
• Sperber Zeev
• Brandt Jason W

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F2201/865

  Monitoring of software · CPC title

• G06F11/3471 Primary

  Address tracing · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title