Capcitive touch panel with simultaneously enabled X- and Y-direction sensor circuits wherein in each sensor circuit the drive line is interdigitated with a plurality of sense lines

Patent metadata

Field	Value
Publication number	US-9262017-B2
Application number	US-79428110-A
Country	US
Kind code	B2
Filing date	Jun 4, 2010
Priority date	Jun 5, 2009
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

There is offered a signal processing circuit of the electrostatic capacity type touch panel which can eliminate duplication of components to reduce a cost of the components. A touch panel 51 is formed on a glass substrate 200 . Sensor circuits 50 A and 50 B are arrayed in a Y direction, and sensor circuits 50 C and 50 D are arrayed in an X direction on the periphery of the touch pane 51 . Serial clock terminals SCL of the sensor circuits 50 A- 50 D are connected to a serial clock line 53 all together, while serial data terminals SDA are connected to a serial data line 54 all together. A microcomputer 52 is disposed on a PCB substrate outside the glass substrate 200 . Data communication can be performed between the microcomputer 52 and the sensor circuits 50 A- 50 D through the serial clock line 53 and the serial data line 54.

First claim

What is claimed is:

1. A signal processing circuit of an electrostatic capacity type touch panel, comprising:
a first sensor circuit having a first drive terminal and a plurality of first sensor input terminals, wherein the first sensor circuit provides a first driving signal at the drive terminal of the first sensor circuit;
a first plurality of sense lines disposed on a substrate, wherein a first sense line of the first plurality of sense lines has a first side, a second side, and a first terminal coupled to a first input terminal of the plurality of first sensor input terminals and a second sense line of the first plurality of sense lines has a first side, a second side, and a first terminal coupled to a second input terminal of the plurality of first sensor input terminals;
a first drive line comprising a first section having a first terminal, a second section having a second terminal, and a third section having a third terminal, the second terminal of the first drive line electrically separated from the third terminal of the first drive line, the first terminal of the first drive line coupled to the drive terminal of the first sensor circuit, the first section of the first drive line adjacent the first side of the first sense line of the first plurality of sense lines, the second section of the first drive line adjacent the second side of the first sense line of the first plurality of sense lines and first side of the second sense line of the first plurality of sense lines;
a second sensor circuit having a drive terminal and a plurality of second sensor input terminals, wherein the second sensor circuit provides a second driving signal at the drive terminal of the second sensor circuit;
a second plurality of sense lines disposed on the substrate and intersecting with the first plurality of sense lines, wherein a first sense line of the second plurality of sense lines has a first side, a second side, and a first terminal coupled to a first input terminal of the second plurality of sense lines;
a second drive line comprising a first section having a first terminal and a second section having a second terminal, the first terminal of the second drive line coupled to the drive terminal of the second sensor circuit, the first section of the second drive line adjacent the first side of the first sense line of the second plurality of sense lines, the second section of the first sense line adjacent the second side of the first sense line of the second plurality of sense lines, the second drive line electrically insulated from the first drive line, wherein the first sensor circuit provides a first driving signal on the first drive line and detects a change in a capacitance between one of the first sense line of the first plurality of sense lines or the second sense line of the first plurality of sense lines and the first drive line and outputting a first detection signal and produces a first digital value that indicates which one of the first plurality of sense lines at which the change in capacitance is detected and wherein the
second sensor circuit provides a second driving signal on the second drive line and detects a change in a capacitance between one of the first sense of the second plurality of sense lines or the second sense line of the second plurality of sense lines and the second drive line and outputting a second detection signal and produces a second digital value that indicates which one of the second plurality of sense lines at which the change in capacitance is detected; and
a bus connected to the first and second sensor circuits, the first and second sensor circuits outputting the first and second detection signals to the bus so that data communication is performed between a master device and the first and second sensor circuits through the bus;
wherein the master device enables the first and second sensor circuits simultaneously via a clock signal coupled to both the first and second sensor circuits, and wherein the master device reads the first and second digital values, respectively, from the first and second sensor circuits serially over the bus.

2. The signal processing circuit of claim 1 , wherein the bus comprises an I 2 C bus.

3. The signal processing circuit of claim 1 , further comprising:
a first drive circuit in the first sensor circuit that supplies a first alternating voltage to the first drive line; and
a second drive circuit in the second sensor circuit that supplies a second alternating voltage to the second drive line.

4. The signal processing circuit of claim 3 , wherein the first and second alternating voltages are clock signals.

5. The signal processing circuit of claim 4 , wherein the first sensor circuit has a first electric charge amplifier having an output based on a capacitance differential between two sense lines of the first plurality of sense lines and the second sensor has a second electric charge amplifier having an output based on a capacitance differential between two sense lines of the second plurality of sense lines, and wherein the digital value for each of the first and second sensor circuits is based on an output value of the electric charge amplifiers of the first and second sensor circuits, respectively.

6. The signal processing circuit of claim 1 , wherein the substrate is glass, the first and second sensor circuits are formed on the glass using chip on glass mounting.

7. The signal processing circuit of claim 1 , wherein the first plurality of sense lines comprises four sense lines, and the second plurality of sense lines comprises four sense lines.

8. The signal processing circuit of claim 1 , further comprising:
a third sensor circuit having a third drive terminal and a plurality of third sensor input terminals, wherein the third sensor circuit provides a third driving signal at the drive terminal of the third sensor circuit;
a third plurality of sense lines oriented in parallel with the first plurality of sense lines, wherein a first sense line of the third plurality of sense lines has a first side, a second side, and a first terminal coupled to a first input terminal of the plurality of third sensor input terminals and a second sense line of the third plurality of sense lines has a first side, a second side, and a first terminal coupled to a second input terminal of the plurality of third sensor input terminals;
a third drive line comprising a first section having a first terminal, a second section having a second terminal, and a third section having a third terminal, the second terminal of the third drive line electrically separated from the third terminal of the third drive line, the first terminal of the third drive line coupled to the drive terminal of the third sensor circuit, the first section of the third drive line adjacent the first side of a third sense line of the third plurality of sense lines, the second section of the third drive line adjacent the second side of the first sense line of the third plurality of sense lines and first side of the second sense line of the third plurality of sense lines;
a fourth sensor circuit having a drive terminal and a plurality of fourth sensor input terminals, wherein the fourth sensor circuit provides a fourth driving signal at the drive terminal of the fourth sensor circuit;
a fourth plurality of sense lines disposed on the substrate, intersecting with the third plurality of sense lines, and oriented in parallel with the second plurality of sense lines, wherein a first sense line of the fourth plurality of sense lines has a first side, a second side, and a first terminal coupled to a first input terminal of the fourth plurality of sense lines;
a fourth drive line comprising a first section having a first terminal and a second section having a second

Assignees

• Kobayashi Kazuyuki
• Suzuki Tatsuya
• Fukai Kumiko
• Kaneta Yasuhiro
• Semiconductor Components Ind

Inventors

• Kobayashi Kazuyuki
• Suzuki Tatsuya
• Fukai Kumiko
• Kaneta Yasuhiro

Classifications

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0416

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F3/0443

  using a single layer of sensing electrodes · CPC title

• G06F3/04166

  Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184) · CPC title

• G06F3/04164

  Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title